ADC12DS080 datasheet(3/33 Pages) TI2

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AGND

ADC12DS080

www.ti.com

SNAS443A – MARCH 2008 – REVISED MARCH 2013

Pin Descriptions and Equivalent Circuits

Pin No.

Symbol

Equivalent Circuit

Description

ANALOG I/O

VINA+

VINB+

Differential analog input pins. The differential full-scale input signal

level is 2VP-P with each input pin signal centered on a common mode

VINA-

voltage, VCM.

VINB-

VRPA

VRPB

VCMOA

VCMOB

These pins should each be bypassed to AGND with a low ESL

(equivalent series inductance) 0.1 µF capacitor placed very close to

the pin to minimize stray inductance. An 0201 size 0.1 µF capacitor

should be placed between VRP and VRN as close to the pins as

possible, and a 1 µF capacitor should be placed in parallel.

VRP and VRN should not be loaded. VCMO may be loaded to 1mA for

VRNA

use as a temperature stable 1.5V reference.

VRNB

It is recommended to use VCMO to provide the common mode

voltage, VCM, for the differential analog inputs.

Reference Voltage. This device provides an internally developed

1.2V reference. When using the internal reference, VREF should be

decoupled to AGND with a 0.1 µF and a 1µF, low equivalent series

VREF

inductance (ESL) capacitor.

This pin may be driven with an external 1.2V reference voltage.

This pin should not be used to source or sink current.

LVDS Driver Bias Resistor is applied from this pin to Analog Ground.

LVDS_Bias

The nominal value is 3.6K

DIGITAL I/O

The clock input pin.

CLK

The analog inputs are sampled on the rising edge of the clock input.

Reset_DLL input. This pin is normally low. If the input clock

frequency is changed abruptly, the internal timing circuits may

Reset_DLL

become unlocked. Cycle this pin high for 1 microsecond to re-lock

the DLL. The DLL will lock in several microseconds after Reset_DLL

is asserted.

This is a four-state pin controlling the input clock mode and output

data format.

OF/DCS = VA, output data format is 2's complement without duty

cycle stabilization applied to the input clock

OF/DCS = AGND, output data format is offset binary, without duty

cycle stabilization applied to the input clock.

OF/DCS

OF/DCS = (2/3)*VA, output data is 2's complement with duty cycle

stabilization applied to the input clock

OF/DCS = (1/3)*VA, output data is offset binary with duty cycle

stabilization applied to the input clock.

Note: This signal has no effect when SPI_EN is high and the SPI

interface is enabled.

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