ADC12DS080

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SNAS443A – MARCH 2008 – REVISED MARCH 2013

Logic and Power Supply Electrical Characteristics

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VDR = +3.0V, Internal VREF =

+1.2V, fCLK = 80 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤

TMAX. All other limits apply for TA = 25°C

(1) (2)

Units

Parameter

Test Conditions

Typical(3)

Limits

(Limits)

DIGITAL INPUT CHARACTERISTICS (CLK, PD_A,PD_B,SCSb,SPI_EN,SCLK,SDI,TEST,WAM,DLC)

VIN(1)

Logical “1” Input Voltage

VD = 3.6V

2.0

V (min)

VIN(0)

Logical “0” Input Voltage

VD = 3.0V

0.8

V (max)

IIN(1)

Logical “1” Input Current

VIN = 3.3V

10

µA

IIN(0)

Logical “0” Input Current

VIN = 0V

−10

µA

CIN

Digital Input Capacitance

5

pF

DIGITAL OUTPUT CHARACTERISTICS (ORA,ORB,SDO,DLL_Lock)

VOUT(1)

Logical “1” Output Voltage

IOUT = −0.5 mA

1.2

V (min)

VOUT(0)

Logical “0” Output Voltage

IOUT = 1.6 mA

0.4

V (max)

+ISC

Output Short Circuit Source Current

VOUT = 0V

−10

mA

−ISC

Output Short Circuit Sink Current

VOUT = VDR

10

mA

COUT

Digital Output Capacitance

5

pF

POWER SUPPLY CHARACTERISTICS

IA

Analog Supply Current

Full Operation

204

230

mA (max)

IDR

Digital Output Supply Current

Full Operation

62

70

mA

Power Consumption

800

900

mW (max)

Power Down Power Consumption

Clock disabled

30

mW

(1)

The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided

current is limited per Note 4. However, errors in the A/D conversion can occur if the input goes above 2.6V or below GND as described

in the Operating Ratings section. See Figure 2.

(2)

With a full scale differential input of 2VP-P , the 12-bit LSB is 488 µV.

(3)

Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical

specifications are not ensured.

Timing and AC Characteristics

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VDR = +3.0V, Internal VREF =

+1.2V, fCLK = 80 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Timing measurements are taken at 50%

of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C

(1) (2)

Units

Parameter

Test Conditions

Typical(3)

Limits

(Limits)

In Single-Lane Mode

65

Maximum Clock Frequency

MHz (max)

In Dual-Lane Mode

80

In Single-Lane Mode

25

Minimum Clock Frequency

MHz (min)

In Dual-Lane Mode

52.5

Single-Lane Mode

7.5

tCONV

Conversion Latency

Dual-Lane, Offset Mode

8

Clock Cycles

Dual-Lane, Word Aligned Mode

9

tAD

Aperture Delay

0.6

ns

tAJ

Aperture Jitter

0.1

ps rms

(1)

The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided

current is limited per Note 4. However, errors in the A/D conversion can occur if the input goes above 2.6V or below GND as described

in the Operating Ratings section. See Figure 2.

(2)

With a full scale differential input of 2VP-P , the 12-bit LSB is 488 µV.

(3)

Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical

specifications are not ensured.

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