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TDA8026ET/C2 Datasheet(PDF) 29 Page - NXP Semiconductors |
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TDA8026ET/C2 Datasheet(HTML) 29 Page - NXP Semiconductors |
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29 / 61 page  TDA8026_1 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. Product data sheet Rev. 1.1 — 30 June 2016 29 of 61 NXP Semiconductors TDA8026 Multiple smart card slot interface IC 8.5.4.8 Bank 1 Register1 (REG[1:0] = 10) card slot 3 (address 03h), card slot 4 (address 04h) and card slot 5 (address 05h) bit allocation 8.5.4.9 Bank 1 Register1 (REG[1:0] = 10) card slot 3 (address 03h), card slot 4 (address 04h) and card slot 5 (address 05h) read/write mode bit descriptions 8.5.4.10 Bank 1 Register1 (REG[1:0] = 11) card slot 3 (address 03h), card slot 4 (address 04h) and card slot 5 (address 05h) bit allocation 8.5.4.11 Bank 1: Bank 1 Register1 (REG[1:0] = 11) card slot 3 (address 03h), card slot 4 (address 04h) and card slot 5 (address 05h) read/write mode bit descriptions 8.5.5 Selection of asynchronous or synchronous mode When the activation sequence starts, the selected card slot on the TDA8026 uses the RSTIN bit value to configure itself for use with asynchronous or synchronous cards. If the RSTIN bit is set to logic 1 at the activation sequence start (the START bit changes from LOW to HIGH), the TDA8026 will manage asynchronous cards. In asynchronous mode, the card slot RST(n) pin is controlled by the corresponding ATR counter (see Section 8.9 on page 36). In synchronous mode, the card slot RST(n) pin is controlled by the corresponding RSTIN bit. The card clock configuration is set by the PWDN bit value at the activation sequence start of the selected card slot (the START bit changed from LOW to HIGH). Table 28. Bank 1 Register1 (REG[1:0] = 10) card slot 3 (address 03h), card slot 4 (address 04h) and card slot 5 (address 05h) bit allocation Bit 7 6 5 4 3 2 1 0 Symbol C[15:8] Access R/W Table 29. Bank 1 Register1 (REG[1:0] = 10) card slot 3 (address 03h), card slot 4 (address 04h) and card slot 5 (address 05h) read/write mode bit descriptions Bit Symbol Description 7 to 0 C[15:8] most significant byte of a programmable 16-bit clock counter. This value applies to all slots. The reset value is A4h. See ATR Section 8.9 “Answer to reset counters” on page 36 Table 30. Bank 1 Register1 (REG[1:0] = 11) card slot 3 (address 03h), card slot 4 (address 04h) and card slot 5 (address 05h) bit allocation Bit 7 6 5 4 3 2 1 0 Symbol C[7:0] Access R/W Table 31. Bank 1: Bank 1 Register1 (REG[1:0] = 11) card slot 3 (address 03h), card slot 4 (address 04h) and card slot 5 (address 05h) read/write mode bit descriptions Bit Symbol Description 7 to 0 C[7:0] least significant byte of a programmable 16-bit clock counter. This value applies to all slots. The reset value is 74h. See Section 8.9 on page 36 |
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