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STM32L496QGI3 Datasheet(PDF) 229 Page - STMicroelectronics |
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STM32L496QGI3 Datasheet(HTML) 229 Page - STMicroelectronics |
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229 / 262 page  DocID029173 Rev 1 229/262 STM32L496xx Electrical characteristics 235 NAND controller waveforms and timings Figure 51 through Figure 54 represent synchronous waveforms, and Table 114 and Table 115 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: • COM.FMC_SetupTime = 0x01 • COM.FMC_WaitSetupTime = 0x03 • COM.FMC_HoldSetupTime = 0x02 • COM.FMC_HiZSetupTime = 0x01 • ATT.FMC_SetupTime = 0x01 • ATT.FMC_WaitSetupTime = 0x03 • ATT.FMC_HoldSetupTime = 0x02 • ATT.FMC_HiZSetupTime = 0x01 • Bank = FMC_Bank_NAND • MemoryDataWidth = FMC_MemoryDataWidth_16b • ECC = FMC_ECC_Enable • ECCPageSize = FMC_ECCPageSize_512Bytes • TCLRSetupTime = 0 • TARSetupTime = 0 In all timing tables, the THCLK is the HCLK clock period. Table 113. Synchronous non-multiplexed PSRAM write timings(1)(2) Symbol Parameter Min Max Unit tw(CLK) FMC_CLK period 2THCLK-0.5 - ns td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 2 td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) THCLK+0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0.5 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 4 td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) 0 - td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 1.5 td(CLKH-NWEH) FMC_CLK high to FMC_NWE high THCLK+1 - td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 3 td(CLKL-NBLL) FMC_CLK low to FMC_NBL low 1.5 - td(CLKH-NBLH) FMC_CLK high to FMC_NBL high THCLK+0.5 - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 - th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 3.5 - 1. CL = 30 pF. 2. Guaranteed by characterization results. |
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