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STM32L496QGI3 Datasheet(PDF) 232 Page - STMicroelectronics |
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STM32L496QGI3 Datasheet(HTML) 232 Page - STMicroelectronics |
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232 / 262 page  Electrical characteristics STM32L496xx 232/262 DocID029173 Rev 1 6.3.29 Camera interface (DCMI) timing specifications Unless otherwise specified, the parameters given in Table 116 for DCMI are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 21, with the following configuration: • DCMI_PIXCLK polarity: falling • DCMI_VSYNC and DCMI_HSYNC polarity: high • Data format: 14 bits • Capacitive load C=30pF Figure 55. DCMI timing diagram Table 116. DCMI characteristics(1) 1. Data based on characterization results, not tested in production. Symbol ParameterMin Max Unit Frequency ratio DCMI_PIXCLK/fHCLK -0.4 DCMI_PIXCLK Pixel clock input - 32 MHz Dpixel Pixel clock input duty cycle 30 70 % tsu(DATA) Data input setup time 4 - ns th(DATA) Data hold time 5 - tsu(HSYNC), tsu(VSYNC) DCMI_HSYNC/DCMI_VSYNC input setup time 3- th(HSYNC), th(VSYNC) DCMI_HSYNC/DCMI_VSYNC input hold time 3 - |
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