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STM32L496QGI3 Datasheet(PDF) 234 Page - STMicroelectronics |
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STM32L496QGI3 Datasheet(HTML) 234 Page - STMicroelectronics |
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234 / 262 page ![]() Electrical characteristics STM32L496xx 234/262 DocID029173 Rev 1 Figure 57. SD default mode Table 118. SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V(1) Symbol Parameter Conditions Min Typ Max Unit fPP Clock frequency in data transfer mode 0 50 MHz - SDIO_CK/fPCLK2 frequency ratio - - 4/3 - tW(CKL) Clock low time fpp =50 MHz 8 10 - ns tW(CKH) Clock high time fpp =50 MHz 8 10 - CMD, D inputs (referenced to CK) in MMC and SD HS mode tISU Input setup time HS fpp =50 MHz 2.5 - - ns tIH Input hold time HS fpp =50 MHz 2.5 - - CMD, D outputs (referenced to CK) in MMC and SD HS mode tOV Output valid time HS fpp =50 MHz - 12 13 ns tOH Output hold time HS fpp =50 MHz 10 - - CMD, D inputs (referenced to CK) in SD default mode tISUD Input setup time SD fpp =25 MHz 3.5 - - ns tIHD Input hold time SD fpp =25 MHz 3 - - CMD, D outputs (referenced to CK) in SD default mode tOVD Output valid default time SD fpp =25 MHz - 3 5 ns tOHD Output hold default time SD fpp =25 MHz 0 - - 1. Guaranteed by characterization results. Table 119. SD / MMC dynamic characteristics, VDD=1.71 V to 1.9 V(1) Symbol Parameter Conditions Min Typ Max Unit fPP Clock frequency in data transfer mode - 0 - 50 MHz - SDIO_CK/fPCLK2 frequency ratio - - - 4/3 - tW(CKL) Clock low time fPP = 50 MHz 8 10 - ns tW(CKH) Clock high time fPP = 50 MHz 8 10 - ns |
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