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UCC24612-2DBVT Datasheet(PDF) 16 Page - Texas Instruments |
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UCC24612-2DBVT Datasheet(HTML) 16 Page - Texas Instruments |
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16 / 38 page ![]() -50mV -150mV 90%TSR(N-1) TSR(N) 90%TSR(N) TSR(N+1) ISR VDS VGATE t t t 16 UCC24612 SLUSCM5A – AUGUST 2017 – REVISED FEBRUARY 2018 www.ti.com Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Feature Description (continued) Figure 18. Forced Proportional Gate-Drive for Deep CCM Operation For Flyback converters, the SR current starts from its maximum amplitude and keeps reducing. Proportional gate drive is only enabled at the later part of the SR current conduction period. However, for other topologies such as LLC or Active Clamp Flyback, the SR current starts from lower amplitude and then increases to a higher amplitude. To prevent the proportional gate drive from being enabled at the beginning of the conduction period, proportional drive is disabled for the first 50% of the SR conduction time, based on the previous cycle SR conduction time. In this way, the proportional drive is always enabled on the current falling slope and minimizes impact on the conduction loss. |
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