UCC24612-2DBVT datasheet(31/38 Pages) TI2

31 / 38 page

UCC24612

CVDD

CREG

SR MOSFET

SR Source

SR Drain

UCC24612

www.ti.com

SLUSCM5A – AUGUST 2017 – REVISED FEBRUARY 2018

Submit Documentation Feedback

10 PCB Layout

10.1 Layout Guidelines

The printed circuit board (PCB) requires careful layout to minimize current loop areas and track lengths,

especially when using single-sided PCBs.

•

Place a ceramic MLCC bypass capacitor as close as possible between VDD and VS, and between REG and

VS.

•

Avoid connecting VD and VS sense points at locations where stray inductance is added to the SR MOSFET

package inductance, as this will tend to turn off the SR prematurely.

•

Run a track from the VD pin directly to the MOSFET drain pad to avoid sensing voltage across the stray

inductance in the SR drain current path.

•

Run a track from the VS pin directly to the MOSFET source pad to avoid sensing voltage across the stray

inductance in the SR source current path. Because this trace shares both the gate driver path and the

MOSFET voltage sensing path, it is recommended to make this trace as short as possible.

•

Run parallel tracks from VG and VS to the SR MOSFET. Include a series gate resistor between VG and SR

MOSFET gate pin to dampen ringing if it is needed.

10.2 Layout Example

Figure 35. PCB Layout for Driving an SR with SO-8 Package

UCC24612-2DBVT Datasheet(PDF) 31 Page - Texas Instruments