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UCC24612-2DBVT Datasheet(PDF) 10 Page - Texas Instruments |
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UCC24612-2DBVT Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 38 page ![]() REG VDD VD START TSD VG VS Adaptive TOFF & DCM ring rejection VTHVGON S Q Q R VTHVGOFF VTHREG Prop-DRV threshold 9.5-V Linear Regulator REG UVLO POWER & FAULT MANGEMENT PROPORTIONAL GATE DRIVE CONTROL GATE DRIVER + ± + ± Turn On Blanking Copyright © 2018, Texas Instruments Incorporated 10 UCC24612 SLUSCM5A – AUGUST 2017 – REVISED FEBRUARY 2018 www.ti.com Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated 7 Detailed Description 7.1 Overview The UCC24612 synchronous rectifier (SR) controller uses drain-to-source voltage sensing to determine the SR MOSFET conduction interval. The SR MOSFET is turned on when VDS exceeds turn-on threshold VTHVGON, and is turned off when VDS falls below VTHVGOFF. The SR conduction voltage drop is continuously monitored and regulated to minimize the conduction loss while allowing the SR to pre-turn-off when operating in continuous conduction mode (CCM) . The extremely fast turn-off comparator and driving circuit ensures the fast turn-off of the SR MOSFET, even in CCM condition. Fixed minimum on-time (tON(min) ) allows the controller to operate up to 1-MHz switching frequency (1 MHz for UCC24612-1, 800 kHz for UCC24612-2). The adaptive minimum off-time control simplifies the design, making the controller suitable for a wide range of applications and switching frequencies, with good immunity to noise caused by parasitic ringing. To minimize the standby power, automatic light-load mode disables the VG pulses when the average switching frequency of the converter becomes lower than fSLEEP (12 kHz typical). When the load increases such that the average switching frequency increases above fWAKE (15 kHz typical), the controller resumes normal SR operation. The wide VDD range and gate driver clamp make the controller ideal for wide output voltage range applications such as USB Power Delivery (USB-PD) adapters, for example. 7.2 Functional Block Diagram |
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