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UCC24612

SLUSCM5A – AUGUST 2017 – REVISED FEBRUARY 2018

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7.4 Device Functional Modes

7.4.1 UVLO Mode

UCC24612 uses the REG pin voltage to detect UVLO instead of the VDD pin voltage. When the REG voltage to

the device has not yet reached the VREGON threshold, or has fallen below the UVLO threshold VREGOFF, the

device operates in the low-power UVLO mode. In this mode, most internal functions are disabled and VDD

current is IVDDstart, typically less than 120 µA. If the REG pin is above 2 V, there is an active pull-down from VG

to VS to prevent SR turn-on due to noise. When the REG pin voltage is less than 2 V, there is a weak pull down

from VG to VS and this also helps prevent false turn on of the SR MOSFET. The device exits UVLO mode when

REG increases above the VREGON threshold.

7.4.2 Standby Mode

Standby mode is a low-power operating mode to help achieve low standby power for the entire power supply.

UCC24612 detects the operating frequency of the SR MOSFET and enters or exits standby mode operation

automatically. REG current reduces to IVDDSTBY level. During standby mode, the majority of the SR control

functions are disabled, except the switching frequency monitoring, REG monitoring and the active pull-down on

the gate driver.

7.4.3 Run Mode

Run mode is the normal operating mode of the controller when not in UVLO mode or standby mode. In this

mode, REG current is higher because all internal control and timing functions are operating and the VG output is

driving the MOSFET for synchronous rectification. REG current is the sum of IVDDRUN plus the average current

necessary to drive the load on the VG output. The VG voltage is automatically adjusted based on the SR

MOSFET drain to source voltage according to the proportional gate drive operation.