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TMS320VC33 Datasheet(PDF) 15 Page - Texas Instruments

Part # TMS320VC33
Description  SMx320VC33 Digital Signal Processor
PDF  53 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

TMS320VC33 Datasheet(HTML) 15 Page - Texas Instruments

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SM320VC33, SMJ320VC33
www.ti.com
SGUS034F – FEBRUARY 2001 – REVISED JUNE 2015
6.23 Switching Characteristics for Loading when XF is Configured as an Output
over recommended operating conditions for loading the XF register when configured as an output pin (see Figure 11)
MIN
MAX
UNIT
tv(H3H-XF)
Valid time, XFx after H3 high
3
ns
6.24 Switching Characteristics for Changing XFx from Output to Input Mode
over recommended operating conditions for changing XFx from output to input mode (see Figure 12)
PARAMETER
MIN
MAX
UNIT
tdis(H3H-XF)
Disable time, XFx after H3 high
5(1)
ns
(1)
Not production tested
6.25 Switching Characteristics for Changing XFx from an Input to an Output
over recommended operating conditions for changing XFx from input to output mode (see Figure 13)
PARAMETER
MIN
MAX
UNIT
td(H3H-XF)
Delay time, H3 high to XFx switching from input to output
3
ns
6.26 Switching Characteristics for RESET
over recommended operating conditions for RESET (see Figure 14)
PARAMETER
MIN(1)
MAX(1)
UNIT
td(EXTCLKH-H1H)
Delay time, EXTCLK high to H1 high
2
7
ns
td(EXTCLKH-H1L)
Delay time, EXTCLK high to H1 low
2
7
td(EXTCLKH-H3L)
Delay time, EXTCLK high to H3 low
2
7
td(EXTCLKH-H3H)
Delay time, EXTCLK high to H3 high
2
7
tdis(H1H-DZ)
Disable time, data (high impedance) from H1 high(2)
6
tdis(H3H-AZ)
Disable time, address (high impedance) from H3 high
6
td(H3H-CONTROLH)
Delay time, H3 high to control signals high
3
td(H1H-RWH)
Delay time, H1 high to R/W high
3
td(H1H-IACKH)
Delay time, H1 high to IACK high
3
tdis(RESETL-ASYNCH)
Disable time, asynchronous reset signals disabled (high impedance) from
6
RESET low(3)
(1)
Not production tested
(2)
High impedance for Dbus is limited to nominal bus keeper ZOUT = 15 kΩ.
(3)
Asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1.
6.27 Switching Characteristics for IACK
over recommended operating conditions for IACK (see Figure 16)
PARAMETER
MIN
MAX
UNIT
td(H1H-IACKL)
Delay time, H1 high to IACK low
–1(1)
3
ns
td(H1H-IACKH)
Delay time, H1 high to IACK high
–1(1)
3
(1)
Not production tested
Copyright © 2001–2015, Texas Instruments Incorporated
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Product Folder Links: SM320VC33 SMJ320VC33



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