TMS320VC33 datasheet(44/53 Pages) TI2

44 / 53 page

SM320VC33, SMJ320VC33

SGUS034F – FEBRUARY 2001 – REVISED JUNE 2015

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9 Power Supply Recommendations

9.1 Power Sequencing Considerations

Though an internal ESD and CMOS latchup protection diode exists between CVDD and DVDD, it should not be

considered a current-carrying device on power up. Use an external Schottky diode to prevent CVDD from

exceeding DVDD by more than 0.7 V. The effect of this diode during power up is that if CVDD is powered up first,

DVDD follows by one diode drop even when the DVDD supply is not active.

Typical systems using LDOs of the same family type for both DVDD and CVDD track each other during power up.

In most cases, this is acceptable; but if a high-impedance pin state is required on power up, the SHZ pin can be

used to asynchronously disable all outputs. RESET should not be used in this case because some signals

require an active clock for RESET to have an effect and the clock may not yet be active. The internal core logic

becomes functional at approximately 0.8 V while the external pin IO becomes active at about 1.5 V.

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Product Folder Links: SM320VC33 SMJ320VC33

TMS320VC33 Datasheet(PDF) 44 Page - Texas Instruments