Command

Decode

SDI

CS

FS

EOC/(INT)

Low Power

12-BIT

SAR ADC

Control Logic

CSTART

PWDN

VCC

GND

REFP

4/2 V

Reference

S/H

OSC

Conversion

Clock

M

U

X

FIFO

12 Bit × 8

CFR

SCLK

SDO

A0

A1

A2

A3

A4

A5

A6

A7

REFM

CMR (4 MSBs)

INT

EXT

DIV

TLV2548-EP

SLAS668 – OCTOBER 2009

www.ti.com

FUNCTIONAL BLOCK DIAGRAM

Table 1. ORDERING INFORMATION(1)

ORDERABLE PART

TOP-SIDE MARKING

TA

PACKAGE (2)

NUMBER

–55°C to 125°C

TSSOP-PW

Tape and Reel of 2000

TLV2548MPWREP

TV2548EP

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com.

(2)

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

Table 2. TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

A0

6

A1

7

Analog signal inputs. The analog inputs are applied to these terminals and are internally

A2

8

multiplexed. The driving source impedance should be less than or equal to 1 k

Ω.

A3

9

xxx

I

A4

10

For a source impedance greater than 1 k

Ω, use the asynchronous conversion start signal

A5

11

CSTART (CSTART low time controls the sampling period) or program long sampling period

A6

12

to increase the sampling time.

A7

13

Chip select. A high-to-low transition on the CS input resets the internal 4-bit counter,

enables SDI, and removes SDO from 3-state within a maximum setup time. SDI is disabled

within a setup time after the 4-bit counter counts to 16 (clock edges) or a low-to-high

CS

20

I

transition of CS whichever happens first.

NOTE: CS falling and rising edges need to happen when SCLK is low for a microprocessor

interface such as SPI.

2

Submit Documentation Feedback

Copyright © 2009, Texas Instruments Incorporated

Product Folder Link(s): TLV2548-EP