Charge

Redistribution

DAC

Control

Logic

_

+

REFM

Ain

ADC Code

TLV2548-EP

SLAS668 – OCTOBER 2009

www.ti.com

Table 2. TERMINAL FUNCTIONS (continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

External reference input or internal reference decoupling (shunt capacitors of 10

μF and

0.1

μF between REFP and REFM). The maximum input voltage range is determined by the

REFP

19

I

difference between the voltage applied to this terminal and the REFM terminal when an

external reference is used.

VCC

5

I

Positive supply voltage

Detailed Description

Analog Inputs and Internal Test Voltages

The 4/8 analog inputs and three internal test inputs are selected by the analog multiplexer depending on the

command entered. The input multiplexer is a break-before-make type to reduce input-to-input noise injection

resulting from channel switching.

Converter

The TLV2548 uses a 12-bit successive approximation ADC utilizing a charge redistribution DAC. Figure 1 shows

a simplified version of the ADC.

The sampling capacitor acquires the signal on Ain during the sampling period. When the conversion process

starts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of charge

from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is balanced,

the conversion is complete and the ADC output code is generated.

Figure 1. Simplified Model of the Successive-Approximation System

Serial Interface

INPUT DATA FORMAT

MSB

LSB

D15

−D12

D11

−D0

Command ID[15:12]

Configuration data field ID[11:0]

Input data is binary. All trailing blanks can be filled with zeros.

OUTPUT DATA FORMAT READ CFR/FIFO READ

MSB

LSB

D15

−D12

D11

−D0

Don’t care

Register content or FIFO content OD[11:0]

4

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