TLV2548-EP

SLAS668 – OCTOBER 2009

www.ti.com

Configuration

Configuration data is stored in one 12–bit configuration register (CFR) (see Table 4 for CFR bit definitions). Once

configured after first power up, the information is retained in the H/W or S/W power down state. When the device

is being configured, a write CFR cycle is issued by the host processor. This is a 16–bit write. If the SCLK stops

after the first eight bits are entered, then the next eight bits can be taken after the SCLK is resumed.

Table 4. TLV2548 Configuration Register (CFR) Bit Definitions

BIT

DEFINITION

Reference select

D11

0: External

1: Internal (Tie REFM to analog ground if the internal reference is selected.)

Internal reference voltage select

D10

0: Internal ref = 4 V

1: internal ref = 2 V

Sample period select

D9

0: Short sampling 12 SCLKs (1x sampling time)

1: Long sampling 24 SCLKs (2x sampling time)

Conversion clock source select

00: Conversion clock = internal OSC

D(8,7)

01: Conversion clock = SCLK

10: Conversion clock = SCLK/4

11: Conversion clock = SCLK/2

Conversion mode select

00: Single shot mode [FIFO not used, D(1,0) has no effect.]

D(6,5)

01: Repeat mode

10: Sweep mode

11: Repeat sweep mode

Sweep auto sequence select

00: 0-1-2-3-4-5-6-7

D(4,3)(1)

01: 0-2-4-6-0-2-4-6

10: 0-0-2-2-4-4-6-6

11: 0-2-0-2-0-2-0-2

EOC/INT - pin function select

D2

0: Pin used as INT

1: Pin used as EOC

FIFO trigger level (sweep sequence length)

00: Full (INT generated after FIFO level 7 filled)

D(1,0)

01: 3/4 (INT generated after FIFO level 5 filled)

10: 1/2 (INT generated after FIFO level 3 filled)

11: 1/4 (INT generated after FIFO level 1 filled)

(1)

These bits only take effect in conversion modes 10 and 11.

Sampling

The sampling period starts after the first four input data are shifted in if they are decoded as one of the

conversion commands. These are select analog input (channels 0 through 7) and select test (channels 1 through

3).

Normal Sampling

When the converter is using normal sampling, the sampling period is programmable. It can be 12 SCLKs (short

sampling) or 24 SCLKs (long sampling). Long sampling helps when SCLK is faster than 10 MHz or when input

source resistance is high.

Extended Sampling

CSTART - An asynchronous (to the SCLK) signal, via dedicated hardware pin, CSTART, can be used in order to

have total control of the sampling period and the start of a conversion. This extended sampling is user defined

and is totally independent of SCLK. While CS is high, the falling edge of CSTART is the start of the sampling

period and is controlled by the low time of CSTART. The minimum low time for CSTART should be at least equal

to the minimum t(SAMPLE). In a select cycle used in mode 01 (REPEAT MODE), CSTART can be started as soon

6

Submit Documentation Feedback

Copyright © 2009, Texas Instruments Incorporated

Product Folder Link(s): TLV2548-EP