TDA7491HV datasheet(36/50 Pages) STMICROELECTRONICS

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8.4.2

Slave mode (external clock)

In order to accept an external clock input the pin ROSC must be left open, that is, floating. This forces pin

SYNCLK to be internally configured as an input as given in table below.

The output switching frequency of the slave devices is:

fSW = fSYNCLK / 2

Table 8. How to set up SYNCLK

Mode

ROSC

SYNCLK

Master

ROSC < 60 kΩ

Output

Slave

Floating (not connected)

Input

Figure 54. Master and slave connection

SYNCLK

ROSC

Rosc

Cosc

ROSC

SYNCLK

39 k



100 nF

Output

Input

TDA7491HV

8.5

Modulation

The output modulation scheme of the BTL is called unipolar pulse width modulation (PWM).

The differential output voltages change between 0 V and +VCC and between 0 V and -VCC.

This is in contrast to the traditional bipolar PWM outputs which change between +VCC

and -VCC. An advantage of this scheme is that it effectively doubles the switching frequency of the differential

output waveform on the load then reducing the current ripple accordingly. The OUTP and OUTN are in the same

phase almost overlapped when the input is zero under this condition, then the switching current is low and the

related losses in the load are low.

In practice, a short delay is introduced between these two outputs in order to avoid the BTL output switching

simultaneously when the input is zero.

Figure below shows the resulting differential output voltage and current when a positive, zero and negative input

signal is applied. The resulting differential voltage on the load has a double frequency with respect to outputs

OUTP and OUTN, resulting in reduced current ripple.

TDA7491HV

Modulation

DS5624 - Rev 10

page 36/50

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