Application information

L5300AH7

16/24

DS6143 Rev 13

3.2

Reset

The reset circuit monitors the output voltage Vo. If the output voltage becomes lower than

Vo_th then Res goes low with a delay time (trr). When the output voltage becomes higher than

Vo_th then Res goes high with a delay time Trd. This delay is obtained by 512 periods of

oscillator. The oscillator period is given by:

Equation 1

Tosc = [(VRhth-VRlth) x Ctr] / Icr + [(VRhth-VRlth) x Ctr] / Idr

and reset pulse delay Trd is given by:

Equation 2

trd = 32 x Tosc

Where:

Icr = 20 µA is an internally generated charge current,

Idr = 20 µA is an internally generated discharge current,

VRhth = 2.5V (typ) and VRlth = 0.95V (typ) are two voltage thresholds,

Ctr is an external capacitor put between Vcr pin and GND.

Figure 24.Reset time diagram

3.3

Enable

L5300AH7 is also provided by an enable input, a high signal switches the regulator ON. In

standby mode the output is disabled and the current consumption of the device (quiescent

current) is less than 10 µA.