L9805E datasheet(49/125 Pages) STMICROELECTRONICS

49 / 125 page

L9805E

On-chip peripherals

49/125

The following procedure is recommended to prevent the OCFi bit from being set between

the time it is read and the write to the OCRi register:

–

Write to the OCHRi register (further compares are inhibited).

–

Read the SR register (first step of the clearance of the OCFi bit, which may be

already set).

–

Write to the OCLRi register (enables the output compare function and clears the

OCFi bit).

Figure 26.

Output compare block diagram

Figure 27.

Output compare timing diagram, internal clock divided by 2

Forced compare output capability

The main purpose of the forced compare output capability is the easily generate a fixed

frequency. The following bits of the CR1 register are used:

–

When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin.

–The OLVi bit has to be toggled in order to toggle the OCMPi pin when it is enabled

(OCiE bit=1).

–

The OCFi bit is then not set by hardware, and thus no interrupt request is generated.

–FOLVLi bits have no effect in either One-Pulse mode or PWM mode.

OUTPUT COMPARE

16-bit

CIRCUIT

OCR1 Register

16 BIT FREE RUNNING

COUNTER

OC1E

CC0

CC1

OC2E

OLVL1

OLVL2

OCIE

(Control Register 1) CR1

(Control Register 2) CR2

OCF2

OCF1

(Status Register) SR

16-bit

OCMP1

OCMP2

Latch

OCR2 Register

FOLV2 FOLV1

INTERNAL CPU CLOCK

TIMER CLOCK

COUNTER

OUTPUT COMPARE REGISTER

COMPARE REGISTER LATCH

OCFi AND OCMPi PIN (OLVLi=1)

CPU

writes FFFF

FFFF

FFFC FFFD FFFE FFFF 0000

FFFB

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