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L9805E Datasheet(PDF) 98 Page - STMicroelectronics |
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L9805E Datasheet(HTML) 98 Page - STMicroelectronics |
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98 / 125 page ![]() On-chip peripherals L9805E 98/125 Figure 49. Example - power bridge waveform, PWM up brake driving mode 5.8.6 Register description The power section is controlled by the microcontroller through the following register: POWER BRIDGE CONTROL STATUS REGISTER (PBCSR) Address: 0021h - Read/Write Reset Value: 00000000 (00h) Bit 0 = EN: Power Bridge enable. On reset the bridge is disabled and OUTL and OUTR are in high impedance condition. Bit 1= PWM_EN: PWM driving enable. When reset the bridge is driven directly by IN1 and IN2 bit (Direct Mode). When set the driving is made by PWM1 and/or PWM2 bit according to the Operation Mode selected by IN1 and IN2 bit. Bit 2= IN1: Left Half Bridge control bit if PWM_EN=0, driving mode selection bit if PWM_EN=1. Bit 3= IN2: Right Half Bridge control bit if PWM_EN=0, driving mode selection bit if PWM_EN=1. PWM1 DIR UL DL UR DR OUTL OUTR 7 0 PIE OVT SC DIR IN2 IN1 PWM_EN EN |
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