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ONET1130EC Datasheet(PDF) 47 Page - Texas Instruments |
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ONET1130EC Datasheet(HTML) 47 Page - Texas Instruments |
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47 / 64 page ![]() ONET1130EC www.ti.com SLLSEJ3A – JUNE 2015 – REVISED JULY 2015 8.6.5.4 TX Register 43 (offset = 0000 0000) [reset = 0h] Figure 65. Core Level Register 43 7 6 5 4 3 2 1 0 0 0 0 0 Reserved R R R R R R R R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; RCLR = Read clear Table 27. TX Registers 43 Field Descriptions Bit Field Type Reset Description TX CDR lock status bit 7 TXCDRLock R 0 1 = TX CDR is not locked 0 = TX CDR is locked Latched low status of bit 7. Cleared when read. 6 TXCDRLock (latched Low) RCLR 0 Latched low bit set to 0 when raw status goes low and keep it low even if raw status goes high. TX fault status bit 5 TX_FLT R 0 1 = TX fault detected 0 = TX fault not detected TX driver disable status bit 4 TX_DRVDIS R 0 1 = TX fault logic disables the driver 0 = TX fault logic does not disable the driver 3:0 – R 0 Reserved Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 47 Product Folder Links: ONET1130EC |
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