AD4084BBCZ datasheet(52/94 Pages) AD

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Data Sheet

AD4084

DIGITAL INTERFACE

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Rev. 0 | 52 of 94

Table 24. GPIO_x_SEL Function Descriptions

GPIO_x_SEL

Function

Description

0000b

Configuration SPI

SDO

Configuration Serial Data Output. This configures the selected GPIO to be the SDO for the configuration SPI.

0001b

FIFO full

FIFO Memory Full Indication Output. This configures the selected GPIO to function as a FIFO full indicator. The FIFO full indicator

is set when the conversion result corresponding to the specified count in the FIFO watermark registers (see the FIFO Watermark

Register section, Address 0x1D and Address 0x1E) is loaded into the data FIFO. The FIFO full status bit is cleared by reading data

from the FIFO, and it is cleared when the first conversion result is moved from the FIFO to the data interface output shift register.

0010b

FIFO read done

FIFO Memory Read Completed Output. This configures the selected GPIO to function as a FIFO read done indicator. The FIFO read

done indicator is cleared by default when the FIFO is first enabled, and each time the last conversion result is moved from the FIFO

into the data interface output shift register. The FIFO read done is cleared when the MSB of the last FIFO result is read on the selected

data interface.

0011b

Filter result ready

Filter Result Ready Output. When the digital filter is enabled, this configures the selected GPIO to function as an indicator that new

data is available to read on the interface. This active low indication allows synchronization between the host and the AD4084 when

utilizing the integrated digital filter to oversample and decimate an incoming signal. The signal is driven low at the end of each filter

decimation period and is driven high again before the next decimated output is ready.

0100b

HI_DTCT

High Threshold Event Output. With threshold detection enabled, this configures the selected GPIO to indicate when the high level

threshold is crossed. The output is active high.

0101b

LO_DTCT

Low Threshold Output. With threshold detection enabled, this configures the selected GPIO to indicate when the low level threshold is

crossed. The output is active high.

0110b

ALERT

Status Alert (Active Low) Output. This configures the selected GPIO to function as the status alert for threshold event detection.

0111b

GPIO data

General-Purpose Output Mode. In this mode, the state of the corresponding GPIO_x_DATA bit in the GPIO Configuration A register

(see the GPIO Configuration A Register section, Address 0x19) is applied to the configured output.

1000b

FILTER_SYNC

Filter Synchronization Input (Active Low). This configures the selected GPIO to function as a synchronization signal for the digital filter.

When held low, this input holds the digital filter in reset.

1001b

EXT_EVENT

External Event Trigger Input. Event triggers when a logic high is detected on the configured GPIO input. This event can be used to

trigger the FIFO.

AD4084BBCZ Datasheet(PDF) 52 Page - Analog Devices

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