AD4084BBCZ datasheet(24/94 Pages) AD

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Data Sheet

AD4084

THEORY OF OPERATION

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Rev. 0 | 24 of 94

more than IOVDD. As a consequence of this architectural decision,

it is necessary to either drive the SPI inputs to ground or to other-

wise leave the inputs floating until VDD33 is greater than IOVDD

− 0.3V. Alternatively, the VDD33 source can be connected to the

device using a series power switch, like the ADP199, configured so

that the switch is open when the source is less than IOVDD − 0.3V,

eliminating the parasitic current path through the digital inputs to

VDD33.

Table 10. Recommended Supply Sequence

1.1 V Supplies (IOVDD and VDD11) Source

Supply Sequence

Internally Generated

1. VDDLDO

2. VDD33

Table 10. Recommended Supply Sequence (Continued)

1.1 V Supplies (IOVDD and VDD11) Source

Supply Sequence

3. Digital inputs

4. Input drive, reference

Externally Generated

1. IOVDD, VDD11

2. VDD33

3. Digital inputs

4. Input drive, reference

To power down the application circuit, the power-up sequence

specified in Table 10 should be reversed.

Figure 42. Power Supply Sequence, Internally Generated IOVDD, VDD11

Figure 43. Power Supply Sequence, Externally Generated IOVDD, VDD11

AD4084BBCZ Datasheet(PDF) 24 Page - Analog Devices