AD4084BBCZ datasheet(26/94 Pages) AD

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Data Sheet

AD4084

THEORY OF OPERATION

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Rev. 0 | 26 of 94

Table 11. Power Saving Operating Modes (Continued)

Operating

Mode

OPERATING_MODES

Bits Value

Description

Effect

Wake-Up Time (Maximum Time to

Normal Mode)

If IOVDD is externally supplied, all GPIOx and SPI data

interface signals are enabled. The SPI configuration

interface is fully enabled. Because the SPI data

interface remains enabled, the user can access data

in the result FIFO (see the Result FIFO section).

The ADC core is powered down. The analog circuitry

remains in reset (ANA_RESET remains asserted), and

no ADC conversions can be performed.

The VDD33 supply can be removed to reduce power.

When in use, the internal VDD11 LDO regulator remains

on.

The internal reference buffer is enabled.

The common-mode output buffer is enabled.

The LVDS interface is disabled.

Sleep

0b11

Low power operating mode

The internal IOVDD LDO regulator is disabled.

180μs

If IOVDD is not externally supplied, all GPIOx and all

LVDS and SPI data interface signals are disabled. For

the SPI configuration interface only, writes to the device

configuration register (see the Device Configuration

(see the Interface Configuration A Register section) are

allowed.

If IOVDD is externally supplied, all GPIOx and SPI data

interface signals are enabled. The SPI configuration

interface is fully enabled. Because the SPI data

interface remains enabled, the user can access data

in the result FIFO (see the Result FIFO section).

The ADC core is powered down. The analog circuitry

remains in reset (ANA_RESET remains asserted), and

no ADC conversions can be performed.

The VDD33 supply can be removed to reduce power.

The internal reference buffer is disabled

When enabled, the internal VDD11 LDO regulator

remains on.

The common-mode output buffer is disabled.

The LVDS interface is disabled.

The SPI data interface remains enabled to access data

in the result FIFO (see the Result FIFO section).

To avoid device damage additional recovery time has to be added

when coming out of the standby or sleep mode. This time is

required from the time when part is back to normal mode and is

counted until the next conversion clock as indicated on the plot

Figure 45.

CONV

Standby/Sleep Mode

Normal Mode

trecover

twake-up

Figure 45. Recovery time after Standby/Sleep Mode

SOFTWARE RESET

This reset method must only be used once the AD4084 is in an idle

state, where conversions are not being clocked, and any existing

conversion is completed.

A software reset is achieved by issuing the following two writes to

the Interface Configuration A register (see the Interface Configura-

tion A Register section, Address 0x00):

1. Set SW_RESET and SW_RESETX bits to 1 by writing 0x81 to

the register.

2. Then, issue another write command that sets either or both of

those bits to 0 to initiate the reset.

AD4084BBCZ Datasheet(PDF) 26 Page - Analog Devices

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