CC115LRGPR datasheet(18/74 Pages) TI2

18 / 74 page

CC115L

SWRS105B – MAY 2011 – REVISED JUNE 2014

www.ti.com

NOTE

The minimum tsp,pd figure in Table 5-1 can be used in cases where the user does not read

the CHIP_RDYn signal. CSn low to positive edge on SCLK when the chip is woken from

power-down depends on the start-up time of the crystal being used. The 150

μs in Table 5-1

is the crystal oscillator start-up time measured on SWRR046 and SWRR045 using crystal

AT-41CD2 from NDK.

5.5.1

Chip Status Byte

When the header byte, data byte, or command strobe is sent on the SPI interface, the chip status byte is

sent by the CC115L on the SO pin. The status byte contains key status signals, useful for the MCU. The

first bit, s7, is the CHIP_RDYn signal and this signal must go low before the first positive edge of SCLK.

The CHIP_RDYn signal indicates that the crystal is running.

Bits 6, 5, and 4 comprise the STATE value. This value reflects the state of the chip. The XOSC and power

to the digital core are on in the IDLE state, but all other modules are in power down. The frequency and

channel configuration should only be updated when the chip is in this state.

The last four bits (3:0) in the status byte contains FIFO_BYTES_AVAILABLE. For these bits to give any

valid information, the R/W bit in the header byte must be set to 0. The FIFO_BYTES_AVAILABLE field

contains the number of bytes that can be written to the TX FIFO. When FIFO_BYTES_AVAILABLE=15, 15

or more bytes can be written.

Table 5-2 gives a status byte summary.

Table 5-2. Status Byte Summary

Bits

Name

Description

Stays high until power and crystal have stabilized. Should always be low when

CHIP_RDYn

using the SPI interface.

Indicates the current main state machine mode

Value

State

Description

IDLE state

000

IDLE

(Also reported for some transitional states

instead of SETTLING or CALIBRATE)

001

Reserved

010

Transmit mode

6:4

STATE[2:0]

011

FSTXON

Fast TX ready

Frequency synthesizer calibration is

100

CALIBRATE

running

101

SETTLING

PLL is settling

110

Reserved

TX FIFO has underflowed. Acknowledge

111

TXFIFO_UNDERFLOW

with SFTX

3:0

FIFO_BYTES_AVAILABLE[3:0]

The number of bytes that can be written to the TX FIFO

Detailed Description

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