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CC115LRGPR Datasheet(PDF) 11 Page - Texas Instruments |
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CC115LRGPR Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 74 page  CC115L www.ti.com SWRS105B – MAY 2011 – REVISED JUNE 2014 4.7 Crystal Oscillator TA = 25°C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using SWRR046 and SWRR045. Parameter Min Typ Max Unit Condition For compliance with modulation bandwidth requirements under EN 300 220 V2.3.1 in the 863 to 870 MHz frequency range it is Crystal frequency 26 26 27 MHz recommended to use a 26 MHz crystal for frequencies below 869 MHz and a 27 MHz crystal for frequencies above 869 MHz. This is the total tolerance including a) initial tolerance, b) crystal loading, c) aging, and d) Tolerance ±40 ppm temperature dependence. The acceptable crystal tolerance depends on RF frequency and channel spacing / bandwidth. Load capacitance 10 13 20 pF Simulated over operating conditions ESR 100 Ω This parameter is to a large degree crystal Start-up time 150 µs dependent. Measured on SWRR046 and SWRR045 using crystal AT-41CD2 from NDK 4.8 Frequency Synthesizer Characteristics TA = 25°C, VDD = 3.0 V if nothing else is stated. All measurement results are obtained using SWRR046 and SWRR045. Minimum figures are given using a 27 MHz crystal. Typical and maximum figures are given using a 26 MHz crystal. Parameter Min Typ Max Unit Condition 26- to 27-MHz crystal. The resolution (in Hz) Programmed frequency resolution 397 FXOSC/2 16 412 Hz is equal for all frequency bands Given by crystal used. Required accuracy (including temperature and aging) depends Synthesizer frequency tolerance ±40 ppm on frequency band and channel bandwidth / spacing RF carrier phase noise –92 dBc/Hz at 50 kHz offset from carrier RF carrier phase noise –92 dBc/Hz at 100 kHz offset from carrier RF carrier phase noise –92 dBc/Hz at 200 kHz offset from carrier RF carrier phase noise –98 dBc/Hz at 500 kHz offset from carrier RF carrier phase noise –107 dBc/Hz at 1 MHz offset from carrier RF carrier phase noise –113 dBc/Hz at 2 MHz offset from carrier RF carrier phase noise –119 dBc/Hz at 5 MHz offset from carrier RF carrier phase noise –129 dBc/Hz at 10 MHz offset from carrier Time from leaving the IDLE state until arriving PLL turn-on or hop time in the FSTXON or TX state, when not 72 75 75 µs (See Table 5-5) performing calibration. Crystal oscillator running. Calibration can be initiated manually or PLL calibration time 685 712 724 µs automatically before entering or after leaving (See Table 5-6) TX 4.9 DC Characteristics TA = 25°C if nothing else stated. Digital Inputs/Outputs Min Max Unit Condition Logic "0" input voltage 0 0.7 V Logic "1" input voltage VDD – 0.7 VDD V Logic "0" output voltage 0 0.5 V For up to 4 mA output current Logic "1" output voltage VDD – 0.3 VDD V For up to 4 mA output current Logic "0" input current N/A –50 nA Input equals 0 V Logic "1" input current N/A 50 nA Input equals VDD Copyright © 2011–2014, Texas Instruments Incorporated Specifications 11 Submit Documentation Feedback Product Folder Links: CC115L |
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