CC115LRGPR datasheet(38/74 Pages) TI2

38 / 74 page

CC115L

SWRS105B – MAY 2011 – REVISED JUNE 2014

www.ti.com

5.16 General Purpose and Test Output Control Pins

The three digital output pins GDO0, GDO1, and GDO2 are general control pins configured with

IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG, and IOCFG2.GDO2_CFG respectively. Table 5-12 shows

the different signals that can be monitored on the GDO pins. These signals can be used as inputs to the

MCU.

GDO1 is the same pin as the SO pin on the SPI interface, thus the output programmed on this pin will

only be valid when CSn is high. The default value for GDO1 is 3-stated which is useful when the SPI

interface is shared with other devices.

The default value for GDO0 is a 135–141 kHz clock output (XOSC frequency divided by 192). Since the

XOSC is turned on at power-on-reset, this can be used to clock the MCU in systems with only one crystal.

When the MCU is up and running, it can change the clock frequency by writing to IOCFG0.GDO0_CFG.

If the IOCFGx.GDOx_CFG setting is less than 0x20 and IOCFGx_GDOx_INV is 0 (1), the GDO0 and

GDO2 pins will be hardwired to 0 (1), and the GDO1 pin will be hardwired to 1 (0) in the SLEEP state.

These signals will be hardwired until the CHIP_RDYn signal goes low.

If the IOCFGx.GDOx_CFG setting is 0x20 or higher, the GDO pins will work as programmed also in

SLEEP state. As an example, GDO1 is high impedance in all states if IOCFG1.GDO1_CFG=0x2E.

Table 5-12. GDOx Signal Selection (x = 0, 1, or 2)

GDOx_CFG

Description

[5:0]

0 (0x00) – 1 Reserved – used for test.

(0x01)

2 (0x02)

Associated to the TX FIFO: Asserts when the TX FIFO is filled at or above the TX FIFO threshold. Deasserts when the TX

FIFO is below the same threshold.

3 (0x03)

Associated to the TX FIFO: Asserts when TX FIFO is full. Deasserts when the TX FIFO is drained below the TX FIFO

threshold.

4 (0x04)

Reserved – used for test.

5 (0x05)

Asserts when the TX FIFO has underflowed. Deasserts when the FIFO is flushed.

6 (0x06)

Asserts when sync word has been sent, and de-asserts at the end of the packet. The pin will de-assert if the TX FIFO

underflows.

7 (0x07) – 9 Reserved - used for test.

(0x09)

10 (0x0A)

Lock detector output. The PLL is in lock if the lock detector output has a positive transition or is constantly logic high. To

check for PLL lock the lock detector output should be used as an interrupt for the MCU.

11 (0x0B)

Serial Clock. Synchronous to the data in synchronous serial mode. Data is sampled by CC 115L115L115L on the rising edge

of the serial clock when GDOx_INV=0.

12 (0x0C)

Serial Synchronous Data Output. Used for synchronous serial mode.

13 (0x0D)

Serial Data Output. Used for asynchronous serial mode.

14 (0x0E) –

Reserved - used for test.

26 (0x1A)

27 (0x1B)

PA_PD. Note: PA_PD will have the same signal level in SLEEP and TX states. To control an external PA in applications

where the SLEEP state is used it is recommended to use GDOx_CFGx=0x2F instead.

28 (0x1D) – Reserved - used for test.

40 (0x28)

41 (0x29)

CHIP_RDYn

42 (0x2A)

Reserved - used for test.

43 (0x2B)

XOSC_STABLE

44 (0x2C) -

Reserved - used for test.

45 (0x2D)

46 (0x2E)

High impedance (3-state)

47 (0x2F)

HW to 0 (HW1 achieved by setting GDOx_INV=1). Can be used to control an external PA.

Detailed Description

Submit Documentation Feedback

Product Folder Links: CC115L

CC115LRGPR Datasheet(PDF) 38 Page - Texas Instruments

CC115LRGPR Datasheet(HTML) 38 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74

Datasheet Download

Link URL