DM505LRBABF datasheet(107/295 Pages) TI2

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CL=

C C

(C +C )

vssa_osc0

Device

xo_osc0

xi_osc0

Crystal

(Optional)

SPRS91v_CLK_02

107

DM505

www.ti.com

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Specifications

5.9.4.1

Input Clocks / Oscillators

•

The source of the internal system clock (SYS_CLK1) could be either:

–

A CMOS clock that enters on the xi_osc0 ball (with xo_osc0 left unconnected on the CMOS clock

case).

–

A crystal oscillator clock managed by xi_osc0 and xo_osc0.

•

The source of the internal system clock (SYS_CLK2) could be either:

–

A CMOS clock that enters on the xi_osc1 ball (with xo_osc1 left unconnected on the CMOS clock

case).

–

A crystal oscillator clock managed by xi_osc1 and xo_osc1.

SYS_CLK1 is received directly from oscillator OSC0. For more information about SYS_CLK1 see Device

TRM, Chapter: Power, Reset, and Clock Management.

5.9.4.1.1 OSC0 External Crystal

An external crystal is connected to the device pins. Figure 5-11 describes the crystal implementation.

Figure 5-11. Crystal Implementation

NOTE

The load capacitors, Cf1 and Cf2 in Figure 5-11, should be chosen such that the below

equation is satisfied. CL in the equation is the load specified by the crystal manufacturer. All

discrete components used to implement the oscillator circuit should be placed as close as

possible to the associated oscillator xi_osc0, xo_osc0, and vssa_osc0 pins.

Figure 5-12. Load Capacitance Equation

The crystal must be in the fundamental mode of operation and parallel resonant. Table 5-16 summarizes

the required electrical constraints.

Table 5-16. OSC0 Crystal Electrical Characteristics

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

Parallel resonance crystal frequency

19.2, 20, 27

MHz

Cf1

Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2

Cf2

Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2

ESR(Cf1,Cf2)

Crystal ESR

100

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