DM505LRBABF datasheet(109/295 Pages) TI2

109 / 295 page

xi_osc0

CK0

CK1

SPRS91v_CLK_04

109

DM505

www.ti.com

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Specifications

Table 5-18. OSC0 Input Clock Electrical Characteristics—Bypass Mode

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

Frequency

19.2, 20, 27

MHz

CIN

Input capacitance

2.184

2.384

2.584

IIN

Input current (3.3V mode)

µA

Table 5-19 details the OSC0 input clock timing requirements.

Table 5-19. OSC0 Input Clock Timing Requirements

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

CK0

1 / tc(xiosc0)

Frequency, xi_osc0

19.2, 20, 27

MHz

CK1

tw(xiosc0)

Pulse duration, xi_osc0 low or high

0.45 × tc(xiosc0)

0.55 × tc(xiosc0)

tj(xiosc0)

Period jitter(1), xi_osc0

0.01 × tc(xiosc0)

tR(xiosc0)

Rise time, xi_osc0

tF(xiosc0)

Fall time, xi_osc0

tj(xiosc0)

Frequency accuracy(2), xi_osc0

Ethernet not used

±200

ppm

Ethernet RGMII using

derived clock

±50

ppm

(1) Period jitter is meant here as follows:

– The maximum value is the difference between the longest measured clock period and the expected clock period

– The minimum value is the difference between the shortest measured clock period and the expected clock period

(2) Crystal characteristics should account for tolerance+stability+aging.

Figure 5-14. xi_osc0 Input Clock

5.9.4.1.3 Auxiliary Oscillator OSC1 Input Clock

SYS_CLK2 is received directly from oscillator OSC1. For more information about SYS_CLK2 see Device

TRM, Chapter: Power, Reset, and Clock Management.

5.9.4.1.3.1 OSC1 External Crystal

An external crystal is connected to the device pins. Figure 5-15 describes the crystal implementation.

DM505LRBABF Datasheet(PDF) 109 Page - Texas Instruments

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