DM505LRBABF datasheet(112/295 Pages) TI2

112 / 295 page

xi_osc1

CK0

CK1

SPRS91v_CLK_07

112

DM505

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Specifications

Table 5-23. OSC1 Input Clock Timing Requirements

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

CK0

1 / tc(xiosc1)

Frequency, xi_osc1

Range from 12 to 38.4

MHz

CK1

tw(xiosc1)

Pulse duration, xi_osc1 low or high

0.45 × tc(xiosc1)

0.55 × tc(xiosc1)

tj(xiosc1)

Period jitter(1), xi_osc1

0.01 × tc(xiosc1)

(3)

tR(xiosc1)

Rise time, xi_osc1

tF(xiosc1)

Fall time, xi_osc1

tj(xiosc1)

Frequency accuracy(2), xi_osc1

Ethernet not used

±200

ppm

Ethernet RGMII using

derived clock

±50

ppm

(1) Period jitter is meant here as follows:

– The maximum value is the difference between the longest measured clock period and the expected clock period

– The minimum value is the difference between the shortest measured clock period and the expected clock period

(2) Crystal characteristics should account for tolerance+stability+aging.

(3) The Period jitter requirement for osc1 can be relaxed to 0.02*tc(xiosc1) under the following constraints:

a. The osc1/SYS_CLK2 clock bypasses all device PLLs

b. The osc1/SYS_CLK2 clock is only used to source the DSS pixel clock outputs

Figure 5-18. xi_osc1 Input Clock

5.9.4.1.4 RC On-die Oscillator Clock

RCOSC_32K_CLK is received directly through a network of resistor and capacitor (an RC network) inside

of the SoC. This RC oscillator do not have good frequency stability. The Frequency range is described in

Table 5-24, which depends on the temperature. For more information about RCOSC_32K_CLK see the

Device TRM, Chapter: Power, Reset, and Clock Management.

Table 5-24. RC On-die Oscillator Clock Frequency Range

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

RCOSC_32K_CLK

Internal RC Oscillator

Range from 28 to 42

kHz

5.9.4.2

Output Clocks

The device provides three output clocks. Summary of these output clocks are as follows:

•

clkout1 - Device Clock output 1. Can be used as a system clock for other devices. The source of the

clkout1 could be either:

–

The input system clock and alternate clock (xi_osc0 or xi_osc1)

–

CORE clock (from CORE output)

–

192-MHz clock (from PER DPLL output)

•

clkout2 - Device Clock output 2. Can be used as a system clock for other devices. The source of the

clkout2 could be either:

–

The input system clock and alternate clock (xi_osc0 or xi_osc1)

–

CORE clock (from CORE output)

–

192-MHz clock (from PER DPLL output)

DM505LRBABF Datasheet(PDF) 112 Page - Texas Instruments

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