TLC6989DYYR datasheet(23/71 Pages) TI2

23 / 71 page

7.4.3 Normal State

To enable the transmission by the CCSI controller, the FLAG_POR needs to be cleared. If the communications

watchdog timer is enabled, and then expires due to a lack of communication, the device enters Failsafe state.

The device can be also forced into Failsafe state anytime in Normal state by setting bit FORCE_FS in register

DEVCTRL to 1. The FORCE_FS bit automatically returns to 0.

7.4.4 Failsafe State

When the device enters the Failsafe state, the TXFFCLR bit is set to stop any ongoing CCSI transmission.

The SPI peripheral is first reset when entering the Failsafe state. Afterwards, the SPI peripheral is kept alive to

allow communication to the device. However, there is no control over the CCSI controller and CCSI peripheral.

This means that when the SPI command starts with FWD, the data is ignored and not stored in the TXFIFO.

The device can quit from Failsafe to Normal state by setting bit EXIT_FS in register DEVCTRL to 1. The

EXIT_FS bit automatically returns to 0. Another method to bring the device to Normal state is by sending the

SOFTRESET_CRC SPI command.

7.5 Programming

The TLC6989 has a serial peripheral interface (SPI) peripheral which is a high-speed synchronous serial input

and output (I/O) port that allows a serial bit stream of 16 bits length to be shifted into and out of the device based

on the externally provided clock rate. The bit stream shifted into the device provides access to the programmable

functions and registers. The interface consists of 4 wires:

• Serial Data In (SDI)

• Serial Data Out (SDO)

• Serial Clock (SCLK)

• Chip Select (CS)

7.5.1 SPI Data Validity

The data on SDI wire must be stable at the rising edge of the SCLK wire. The data on SDO shifts out at the

falling edge of the SCLK wire. SDO can be forced to be disabled by the bit SPI_SDO_DIS in the SPICTRL

bus. When no data is shifted into the device, the SCLK wire is expected to be logic LOW.

7.5.2 Chip Select (CS) and SPI Reset Control

The CS signal provides the ability to gate any spurious clock and data pulses. A HIGH logic signal on CS blocks

the peripheral to receive data. This prevents the SPI peripheral from losing synchronization with the controller. TI

does not recommend that the CS always be tied to the active state.

If the SPI peripheral does ever lose synchronization with the controller, providing a HIGH logic signal on CS

resets SPI peripheral including the bit counter. Another method is to stop the SCLK and wait longer than the

setting of the field SPI_RST_TIMEOUT_CFG in the SPICTRL register. This timeout starts counting from the first

rising clock edge of SCLK when the SPI peripheral is expecting the command word.

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TLC6989

SLVSHF5 – NOVEMBER 2024

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TLC6989DYYR Datasheet(PDF) 23 Page - Texas Instruments