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M58PR512LE Datasheet(PDF) 10 Page - Numonyx B.V |
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M58PR512LE Datasheet(HTML) 10 Page - Numonyx B.V |
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10 / 123 page  Description M58PR512LE, M58PR001LE 10/123 The M58PRxxxLE features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When VPP ≤VPPLK all blocks are protected against program or erase. All blocks are locked at power-up. In addition to the main memory array, the M58PRxxxLE features an extended flash array (EFA) divided into 4 blocks of 64 Kbits each. The EFA blocks are accessed through a separate set of commands. The operations available in the EFA blocks are asynchronous read (in non-page mode), single word program, erase and block locking. See Section 4: Command interface for details of the EFA commands set. See Table 4 for an extended flash array memory map. Table 18 and Table 19 describe the simultaneous operations allowed in the EFA blocks and the main memory array. The device includes 17 protection registers and 2 protection register locks, one for the first protection register and the other for the 16 OTP (one-time-programmable) protection registers of 128 bits each. The first protection register is divided into two areas: a 64-bit area containing a unique device number written by ST, and a 64-bit area one-time-programmable by the user. The user programmable area can be permanently protected. Figure 6, shows the Protection Register memory map. The memory is available in TFBGA105 or TFBGA107 packages, and is supplied with all the bits erased (set to ’1’). Figure 1. Logic diagram 1. Amax is equal to A24 in the M58PR512LE and to A25 in the M58PR001LE. AI12816c A0-Amax(1) W DQ0-DQ15 VDD M58PR512LE M58PR001LE E VSS 16 G RP WP VDDQ VPP L K WAIT VSSQ DPD |
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