KMB-001LEVALZ datasheet(19/33 Pages) RENESAS

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ISLA224P12

FN7983 Rev.4.01

Page 19 of 32

Apr 8, 2024

Over-Range Indicator

The over-range (OR) bit is asserted when the output code reaches

positive full-scale (e.g. 0xFFF in offset binary mode). The output

code does not wrap around during an over-range condition. The

OR bit is updated at the sample rate.

Power Dissipation

The power dissipated by the ISLA224P12 is primarily dependent

on the sample rate and the output modes: LVDS vs CMOS and

DDR vs SDR. There is a static bias in the analog supply, while the

remaining power dissipation is linearly related to the sample

rate. The output supply dissipation changes to a lesser degree in

LVDS mode, but is more strongly related to the clock frequency in

CMOS mode.

Nap/Sleep

Portions of the device may be shut down to save power during

times when operation of the A/D is not required. Two power saving

modes are available: Nap, and Sleep. Nap mode reduces power

dissipation to <103mW while Sleep mode reduces power

dissipation to <19mW.

All digital outputs (Data, CLKOUT and OR) are placed in a high

impedance state during Nap or Sleep. The input clock should

remain running and at a fixed frequency during Nap or Sleep, and

CSB should be high. Recovery time from Nap mode will increase

if the clock is stopped, since the internal DLL can take up to

104µs to regain lock at 125MSPS.

By default after the device is powered on, the operational state is

controlled by the NAPSLP pin as shown in Table 3.

The power-down mode can also be controlled through the SPI

port, which overrides the NAPSLP pin setting. Details on this are

contained in “Serial Peripheral Interface” on page 22.

Data Format

Output data can be presented in three formats: two’s

complement(default), Gray code and offset binary. The data

format can also be controlled through the SPI port, by writing to

address 0x73. Details on this are contained in “Serial Peripheral

Interface” on page 22.

Offset binary coding maps the most negative input voltage to

code 0x000 (all zeros) and the most positive input to 0xFFF (all

ones). Two’s complement coding simply complements the MSB

of the offset binary representation.

When calculating Gray code the MSB is unchanged. The

remaining bits are computed as the XOR of the current bit

position and the next most significant bit. Figure 35 shows this

operation.

Converting back to offset binary from Gray code must be done

recursively, using the result of each bit for the next lower bit as

shown in Figure 36.

Mapping of the input voltage to the various data formats is

shown in Table 4.

Clock Divider Synchronous Reset

An output clock (CLKOUTP, CLKOUTN) is provided to facilitate

latching of the sampled data. The output clock frequency is

equal to the input clock frequency divided by the internal clock

divider setting (see “Clock Input” on page 18).

TABLE 3. NAPSLP PIN SETTINGS

NAPSLP PIN

MODE

AVSS

Normal

Float

Sleep

AVDD

Nap

TABLE 4. INPUT VOLTAGE TO OUTPUT CODE MAPPING

INPUT

VOLTAGE

OFFSET BINARY

TWO’S

COMPLEMENT

GRAY CODE

–Full Scale 00 0000 0000 0000 10 0000 0000 0000 00 0000 0000 0000

–Full Scale

+ 1LSB

00 0000 0000 0001 10 0000 0000 0001 00 0000 0000 0001

Mid–Scale 10 0000 0000 0000 00 0000 0000 0000 11 0000 0000 0000

+Full Scale

– 1LSB

11 1111 1111 1110 01 1111 1111 1110 10 0000 0000 0001

+Full Scale 11 1111 1111 1111 01 1111 1111 1111 10 0000 0000 0000

FIGURE 35. BINARY TO GRAY CODE CONVERSION

BINARY

GRAY CODE

• • • •

FIGURE 36. GRAY CODE TO BINARY CONVERSION

BINARY

GRAY CODE

• • • •

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