ISLA224P12

FN7983 Rev.4.01

Page 28 of 32

Apr 8, 2024

73

output_mode_A

Output Mode [7:5]

000 = LVDS 3mA (Default)

001 = LVDS 2mA

100 = LVCMOS

Other codes = Reserved

Output Format [2:0]

000 = Two’s Complement (Default)

010 = Gray Code

100 = Offset Binary

Other codes = Reserved

00h

NOT reset by

Soft Reset

74

output_mode_B

DLL Range

0 = Fast

1 = Slow

Default=’0

’

00h

NOT reset by

Soft Reset

75-B5

Reserved

Reserved

B6

cal_status

Calibration

Done

Read Only

B7-BF

Reserved

C0

test_io

Output Test Mode [7:4]

User Test Mode [2:0]

0 = user pattern 1-2

1 = cycle pattern 1 through 4

2 = cycle pattern 1 through 6

3 = cycle pattern 1 through 8

4-7 = NA

00h

0 = Off (Note 14)

1 = Midscale Short

2 = +FS Short

3 = -FS Short

4 = Checkerboard (Note 15)

5-6 = Reserved

7 = All on/ off (Note 16)

8 = User Pattern (1 to 8 deep)

9 = Reserved

10 = Ramp

11-15 = Reserved

C1

user_patt1_lsb

B7

B6

B5

B4

B3

B2

B1

B0

0x00

C2

user_patt1_msb

B15

B14

B13

B12

B11

B10

B9

B8

00h

C3

user_patt2_lsb

B7

B6

B5

B4

B3

B2

B1

B0

00h

C4

user_patt2_msb

B15

B14

B13

B12

B11

B10

B9

B8

00h

C5

user_patt3_lsb

B7

B6

B5

B4

B3

B2

B1

B0

00h

C6

user_patt3_msb

B15

B14

B13

B12

B11

B10

B9

B8

00h

C7

user_patt4_lsb

B7

B6

B5

B4

B3

B2

B1

B0

00h

C8

user_patt4_msb

B15

B14

B13

B12

B11

B10

B9

B8

00h

C9

user_patt5_lsb

B7

B6

B5

B4

B3

B2

B1

B0

00h

CA

user_patt5_msb

B15

B14

B13

B12

B11

B10

B9

B8

00h

CB

user_patt6_lsb

B7

B6

B5

B4

B3

B2

B1

B0

00h

CC

user_patt6_msb

B15

B14

B13

B12

B11

B10

B9

B8

00h

CD

user_patt7_lsb

B7

B6

B5

B4

B3

B2

B1

B0

00h

CE

user_patt7_msb

B15

B14

B13

B12

B11

B10

B9

B8

00h

CF

user_patt8_lsb

B7

B6

B5

B4

B3

B2

B1

B0

00h

D0

user_patt8_msb

B15

B14

B13

B12

B11

B10

B9

B8

00h

D1-FD

Reserved

Reserved

FE

Offset/Gain_Adjust_Enable

Enable

‘1’=Enable

00h

FF

Reserved

NOTES:

14. During Calibration xCCCC (MSB justified) is presented at the output data bus, toggling on the LSB (and higher) data bits occurs at completion of

calibration. This behavior can be used as an option to determine calibration state.

15. Use test_io = 0x41 for Checkerboard outputs on DDR Outputs.

16. Use test_io = 0x71 for all ones/zeroes outputs on DDR Outputs.

SPI Memory Map (Continued)

ADDR.

(Hex)

PARAMETER NAME

BIT 7

(MSB)

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

(LSB)

DEF. VALUE

(HEX)