KMB-001LEVALZ datasheet(23/33 Pages) RENESAS

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ISLA224P12

FN7983 Rev.4.01

Page 23 of 32

Apr 8, 2024

Figures 42 and 43 illustrate the timing relationships for 2-byte

and N-byte transfers, respectively. The operation for a 3-byte

transfer can be inferred from these diagrams.

SPI Configuration

ADDRESS 0X00: CHIP_PORT_CONFIG

Bit ordering and SPI reset are controlled by this register. Bit order

can be selected as MSB to LSB (MSB first) or LSB to MSB (LSB

first) to accommodate various micro controllers.

Bit 7 SDO Active

Bit 6 LSB First

Setting this bit high configures the SPI to interpret serial data

as arriving in LSB to MSB order.

Bit 5 Soft Reset

Setting this bit high resets all SPI registers to default values.

Bit 4 Reserved

This bit should always be set high.

Bits 3:0 These bits should always mirror bits 4:7 to avoid

ambiguity in bit ordering.

ADDRESS 0X02: BURST_END

If a series of sequential registers are to be set, burst mode can

improve throughput by eliminating redundant addressing. The

burst is ended by pulling the CSB pin high. Setting the burst_end

address determines the end of the transfer. During a write

operation, the user must be cautious to transmit the correct

number of bytes based on the starting and ending addresses.

Bits 7:0 Burst End Address

This register value determines the ending address of the burst

data.

Device Information

ADDRESS 0X08: CHIP_ID

ADDRESS 0X09: CHIP_VERSION

The generic die identifier and a revision number, respectively, can

be read from these two registers.

Device Configuration/Control

A common SPI map, which can accommodate single-channel or

multi-channel devices, is used for all Renesas A/D products.

ADDRESS 0X20: OFFSET_COARSE_ADC0

ADDRESS 0X21: OFFSET_FINE_ADC0

The input offset of the A/D core can be adjusted in fine and

coarse steps. Both adjustments are made via an 8-bit word as

detailed in Table 6. The data format is twos complement.

The default value of each register will be the result of the

self-calibration after initial power-up. If a register is to be

incremented or decremented, the user should first read the

back to the same register. Bit 0 in register 0xFE must be set high

to enable updates written to 0x20 and 0x21 to be used by the

ADC (see description for 0xFE).

ADDRESS 0X22: GAIN_COARSE_ADC0

ADDRESS 0X23: GAIN_MEDIUM_ADC0

ADDRESS 0X24: GAIN_FINE_ADC0

Gain of the A/D core can be adjusted in coarse, medium and fine

steps. Coarse gain is a 4-bit adjustment while medium and fine

are 8-bit. Multiple Coarse Gain Bits can be set for a total

adjustment range of ±4.2%. (‘0011’ @ -4.2% and ‘1100’ @ +4.2%)

It is recommended to use one of the coarse gain settings (-4.2%,

-2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and fine-tune the gain using the

registers at 0x0023 and 0x24.

The default value of each register will be the result of the

self-calibration after initial power-up. If a register is to be

incremented or decremented, the user should first read the

back to the same register. Bit 0 in register 0xFE must be set high

to enable updates written to 0x23 and 0x24 to be used by the

ADC (see description for 0xFE).

4 or more

TABLE 5. BYTE TRANSFER SELECTION (Continued)

[W1:W0]

BYTES TRANSFERRED

TABLE 6. OFFSET ADJUSTMENTS

PARAMETER

0x20[7:0]

COARSE OFFSET

0x21[7:0]

FINE OFFSET

Steps

255

–Full Scale (0x00)

-133LSB (-47mV)

-5LSB (-1.75mV)

Mid–Scale (0x80)

0.0LSB (0.0mV)

0.0LSB

+Full Scale (0xFF)

+133LSB (+47mV)

+5LSB (+1.75mV)

Nominal Step Size

1.04LSB (0.37mV)

0.04LSB (0.014mV)

TABLE 7. COARSE GAIN ADJUSTMENT

0x22[3:0] core 0

0x26[3:0] core 1

NOMINAL COARSE GAIN ADJUST

(%)

Bit3

+2.8

Bit2

+1.4

Bit1

-2.8

Bit0

-1.4

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