AM6421 datasheet(89/273 Pages) TI2

89 / 273 page

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The functionality of these pins is controlled by SERDES0_LN0_CTRL_LANE_FUNC_SEL.

5.3.22 System and Miscellaneous

5.3.22.1 Boot Mode Configuration

5.3.22.1.1 MAIN Domain

Table 5-63. Sysboot Signal Descriptions

SIGNAL NAME [1]

SIGNAL

TYPE [2]

DESCRIPTION [3]

ALV/ANI PIN [4]

BOOTMODE00

Bootmode pin 0

T20

BOOTMODE01

Bootmode pin 1

U21

BOOTMODE02

Bootmode pin 2

T18

BOOTMODE03

Bootmode pin 3

U20

BOOTMODE04

Bootmode pin 4

U18

BOOTMODE05

Bootmode pin 5

U19

BOOTMODE06

Bootmode pin 6

V20

BOOTMODE07

Bootmode pin 7

V21

BOOTMODE08

Bootmode pin 8

V19

BOOTMODE09

Bootmode pin 9

T17

BOOTMODE10

Bootmode pin 10

R16

BOOTMODE11

Bootmode pin 11

W20

BOOTMODE12

Bootmode pin 12

W21

BOOTMODE13

Bootmode pin 13

V18

BOOTMODE14

Bootmode pin 14

Y21

BOOTMODE15

Bootmode pin 15

Y20

5.3.22.2 Clock

5.3.22.2.1 MCU Domain

Table 5-64. MCU Clock Signal Descriptions

SIGNAL NAME [1]

SIGNAL

TYPE [2]

DESCRIPTION [3]

ALV/ANI PIN [4]

MCU_OSC0_XI

High frequency oscillator input

C21

MCU_OSC0_XO

High frequency oscillator output

B20

5.3.22.3 System

5.3.22.3.1 MAIN Domain

Table 5-65. System Signal Descriptions

SIGNAL NAME [1]

SIGNAL

TYPE [2]

DESCRIPTION [3]

ALV/ANI PIN [4]

CLKOUT0

RMII Clock Output (50MHz). This pin is used for clock

source to the external PHY and must be routed back to the

RMII_REF_CLK pin for proper device operation.

A19, U13

EXTINTn

External Interrupt

C19

EXT_REFCLK1

External clock input to Main domain

A19

OBSCLK0

Observation clock output for test and debug purposes only

D17

PORz_OUT

Main domain POR status output

E17

RESETSTATz

Main domain warm reset status output

F16

RESET_REQz

Main domain external warm reset request input

E18

SYSCLKOUT0

SYSCLK0 output from Main PLL controller (divided by 6)

for test and debug purposes only

C17

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AM6442, AM6441, AM6422, AM6421, AM6412, AM6411

SPRSP56J – JANUARY 2021 – REVISED JUNE 2026

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