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AM2431BSDGHIALVR. Datasheet(PDF) 5 Page - Texas Instruments |
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AM2431BSDGHIALVR. Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 282 page  3.1 Functional Block Diagram Figure 3-1 is the functional block diagram for the device. Note Refer to the AM243x SW Build Sheet to understand which device features are currently supported by TI Software Development Kits (SDKs). Industrial Connectivity System Memory Security A 243x M AM243x_FBD 2 MB SRAM with ECC DDR4/LPDDR4 with inline ECC 2x MMCSD AES MD5 SHA 3DES PKA DRBG Secure Boot System Services 12x GP Timers 4x WWDT Sync Manager 3x EQEP 3x ECAP 9x EPWM 4x I2C GPIO 5x MCSPI 1x ADC 7x UART PCIe 1x Single lane Gen 2 GPMC / ELM 2x FSITX 6x FSIRX OSPI or QSPI 2x CAN-FD 1x USB 3.1 DRD 3-port Gb Ethernet General Connectivity 2x I2C GPIO 2x MCSPI 2x UART Isolated Connectivity (A) (for use with Cortex-M4F) 128KB TCM Arm Cortex -R5F ® 128KB TCM Arm Cortex -R5F ® Arm Cortex -R5F ® Arm Cortex -R5F ® Arm ® Cortex -M4F 256KB SRAM Real-time cores Isolated core (A) (C) (B) (C) PRU-ICSSG 2x RGMII/MII 18x 24 PWMs 1x UART 6x Encoder 1x ECAP 40 Real-Time GPIOs PRU-ICSSG 2x RGMII/MII 18x 24 PWMs 1x UART 6x Encoder 1x ECAP 40 Real-Time GPIOs A. Isolation of peripherals and M4F core is an optional feature. MCU domain resources are shared across the SoC when in non-isolated configuration. B. One port is connected internally and not routed to any external pins. C. USB3.1 and PCIe share a common SERDES PHY lane. USB will be limited to non-SuperSpeed modes when using the SERDES PHY for PCIe. Figure 3-1. Functional Block Diagram www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: AM2434 AM2432 AM2431 |
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