AM2431BSDGHIALVR. datasheet(75/282 Pages) TI2

75 / 282 page

Table 5-43. GPMC0 Signal Descriptions (continued)

SIGNAL NAME [1] ((2))

SIGNAL

TYPE [2]

DESCRIPTION [3]

ALV/ANI PIN [4]

ALX PIN [4]

GPMC0_AD21

GPMC Data 21 Input/Output in A/D non-multiplexed mode and

additionally Address 22 Output in A/D multiplexed mode

V13

U14

GPMC0_AD22

GPMC Data 22 Input/Output in A/D non-multiplexed mode and

additionally Address 23 Output in A/D multiplexed mode

AA7

GPMC0_AD23

GPMC Data 23 Input/Output in A/D non-multiplexed mode and

additionally Address 24 Output in A/D multiplexed mode

U13

V13

GPMC0_AD24

GPMC Data 24 Input/Output in A/D non-multiplexed mode and

additionally Address 25 Output in A/D multiplexed mode

W13

Y13

GPMC0_AD25

GPMC Data 25 Input/Output in A/D non-multiplexed mode and

additionally Address 26 Output in A/D multiplexed mode

U15

W16

GPMC0_AD26

GPMC Data 26 Input/Output in A/D non-multiplexed mode and

additionally Address 27 Output in A/D multiplexed mode

U14

W13

GPMC0_AD27

GPMC Data 27 Input/Output in A/D non-multiplexed mode and

additionally Address 28 Output in A/D multiplexed mode

AA8

GPMC0_AD28

GPMC Data 28 Input/Output in A/D non-multiplexed mode and

additionally Address 29 Output in A/D multiplexed mode

GPMC0_AD29

GPMC Data 29 Input/Output in A/D non-multiplexed mode and

additionally Address 30 Output in A/D multiplexed mode

GPMC0_AD30

GPMC Data 30 Input/Output in A/D non-multiplexed mode and

additionally Address 31 Output in A/D multiplexed mode

AA9

AA7

GPMC0_AD31

GPMC Data 31 Input/Output in A/D non-multiplexed mode and

additionally Address 0 Output in A/D multiplexed mode

GPMC0_BE0n_CLE

GPMC Lower-Byte Enable (active low) or Command Latch

Enable

P17

GPMC0_BE1n

GPMC Upper-Byte Enable (active low)

T19

P21

GPMC0_BE2n

GPMC Upper-Byte Enable (active low)

GPMC0_BE3n

GPMC Upper-Byte Enable (active low)

AA14

GPMC0_CSn0

GPMC Chip Select 0 (active low)

R19

GPMC0_CSn1

GPMC Chip Select 1 (active low)

R20

GPMC0_CSn2

GPMC Chip Select 2 (active low)

P19

GPMC0_CSn3

GPMC Chip Select 3 (active low)

R21

GPMC0_WAIT0

GPMC External Indication of Wait

W19

GPMC0_WAIT1

GPMC External Indication of Wait

Y18

(1)

The GPMC0_FCLK_MUX signal is not supported by the ALX packaged device. See AM243x_ALX Package - Unsupported Interfaces

and Signals for additional details.

(2)

The GPMC0 interface is not supported by the ALX packaged devices. See AM243x_ALX Package - Unsupported Interfaces and

Signals for additional details.

www.ti.com

AM2434, AM2432, AM2431

SPRSP65J – APRIL 2021 – REVISED JUNE 2026

Submit Document Feedback

Product Folder Links: AM2434 AM2432 AM2431

AM2431BSDGHIALVR. Datasheet(PDF) 75 Page - Texas Instruments

AM2431BSDGHIALVR. Datasheet(HTML) 75 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL