M58BW016DB datasheet(17/63 Pages) STMICROELECTRONICS

17 / 63 page

17/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

Table 5. Asynchronous Read Electronic Signature Operation

Note: 1. x= B or D version of the device.

2. BCR= Burst Configuration Register.

Synchronous Bus Operations

For synchronous bus operations refer to Table 6

together with the following text.

Synchronous Burst Read. Synchronous Burst

Read operations are used to read from the memo-

ry at specific times synchronized to an external ref-

erence clock. The burst type, length and latency

can be configured. The different configurations for

Synchronous Burst Read operations are de-

scribed in the Burst Configuration Register sec-

tion. Refer to Figures 5 and 6 for examples of

synchronous burst operations.

In continuous burst read, one burst read operation

can access the entire memory sequentially by

keeping the Burst Address Advance B at VIL for

the appropriate number of clock cycles. At the end

of the memory address space the burst read re-

starts from the beginning at address 000000h.

A valid Synchronous Burst Read operation begins

when the Burst Clock is active and Chip Enable

and Latch Enable are Low, VIL. The burst start ad-

dress is latched and loaded into the internal Burst

Address Counter on the valid Burst Clock K edge

(rising or falling depending on the value of M6) or

on the rising edge of Latch Enable, whichever oc-

curs first.

After an initial memory latency time, the memory

outputs data each clock cycle (or two clock cycles

depending on the value of M9). The Burst Address

Advance B input controls the memory burst output.

The second burst output is on the next clock valid

edge after the Burst Address Advance B has been

pulled Low.

Valid Data Ready, R, monitors if the memory burst

boundary is exceeded and the Burst Controller of

the microprocessor needs to insert wait states.

When Valid Data Ready is Low on the active clock

edge, no new data is available and the memory

does not increment the internal address counter at

the active clock edge even if Burst Address Ad-

vance, B, is Low.

Valid Data Ready may be configured (by bit M8 of

Burst Configuration Register) to be valid immedi-

ately at the valid clock edge or one data cycle be-

fore the valid clock edge.

Synchronous Burst Read will be suspended if

Burst Address Advance, B, goes High, VIH.

If Output Enable is at VIL and Output Disable is at

VIH, the last data is still valid.

If Output Enable, G, is at VIH or Output Disable,

GD, is at VIL, but the Burst Address Advance, B, is

at VIL the internal Burst Address Counter is incre-

mented at each Burst Clock K valid edge.

The Synchronous Burst Read timing diagrams

and AC Characteristics are described in the AC

and DC Parameters section. See Figures 14, 15,

16 and 17, and Table 20.

Synchronous Burst Read Suspend. During

Synchronous Burst Read operation it is possible to

suspend the operation, freeing the data bus for

other higher priority devices.

A valid Synchronous Burst Read operation is sus-

pended when both Output Enable and Burst Ad-

dress Advance are High, VIH. The Burst Address

Advance going High, VIH, stops the burst counter

and the Output Enable going High, VIH, inhibits the

data outputs. The Synchronous Burst Read oper-

ation can be resumed by setting Output Enable

Low.

Code

Device

A18-A0

DQ31-DQ0

Manufacturer

All

VIL

VIH

00000h

00000020h

Device

M58BW016xT(1)

VIL

VIH

00001h

00008836h

M58BW016xB(1)

VIL

VIH

00001h

00008835h

Burst Configuration

VIL

VIH

00005h

BCR (2)

M58BW016DB Datasheet(PDF) 17 Page - STMicroelectronics

M58BW016DB Datasheet(HTML) 17 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

Datasheet Download

Link URL