M58BW016DB datasheet(20/63 Pages) STMICROELECTRONICS

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M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

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Table 7. Burst Configuration Register

Note: 1. 4 - 2 - 2 - 2 is not allowed.

2. X latencies can be calculated as: (tAVQV – tLLKH + tQVKH) + tSYSTEM MARGIN < (X -1) tK. (X is an integer number from 4 to 8 and tK

is the clock period).

3. Y latencies can be calculated as: tKHQV + tSYSTEM MARGIN + tQVKH < Y tK.

4. tSYSTEM MARGIN is the time margin required for the calculation.

Bit

Description

Value

Description

M15

Read Select

Synchronous Burst Read

Asynchronous Read (Default at power-on)

M14

Reserved

M13-M11

X-Latency (2)

001

Reserved

010

4, 4-1-1-1 (1)

011

5, 5-1-1-1, 5-2-2-2

100

6, 6-1-1-1, 6-2-2-2

101

7, 7-1-1-1, 7-2-2-2

110

8, 8-1-1-1, 8-2-2-2

M10

Reserved

Y-Latency (3)

One Burst Clock cycle

Two Burst Clock cycles

Valid Data Ready

R valid Low during valid Burst Clock edge

R valid Low one data cycle before valid Burst Clock edge

Burst Type

Interleaved

Sequential

Valid Clock Edge

Falling Burst Clock edge

Rising Burst Clock edge

M5-M4

Reserved

Wrapping

Wrap

No wrap

M2-M0

Burst Length

001

4 Double-Words

010

8 Double-Words

111

Continuous

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