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M7040N Datasheet(PDF) 123 Page - STMicroelectronics |
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M7040N Datasheet(HTML) 123 Page - STMicroelectronics |
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123 / 159 page ![]() 123/159 M7040N Figure 92. Timing Diagram of LEARN on Device 7: TLSZ = 01 Table 51. Latency of SRAM WRITE Cycle from Second Cycle of LEARN Instruction # of devices Max Table Size Latency in CLK Cycles 1 (TLSZ = 00) 16K x 72-bit 4 2–8 (TLSZ = 01) 128K x 72-bit 5 2–31 (TLSZ = 10) 496K x 72-bit 6 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 7 Cycle 6 Cycle 8 Cycle 10 Cycle 9 CLK2X CMDV CMD[1:0] CE_L WE_L OE_L SSV SSF SADR[23:0] CMD[10:2] PHS_L AI04734 DQ TLSZ = 01, LRAM = 1, LDEV = 1 Learn1 Learn2 Comp1 1A 1B Comp2 X X X X X X X X 1 1 0 0 0 z z 1 1 1 z z 1 z 0 1 z z |
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