M7040N datasheet(124/159 Pages) STMICROELECTRONICS

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M7040N

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DEPTH-CASCADING

The search engine application can depth-cascade

the device to various table sizes of different widths

(e.g., 72-bit, 144-bit, and 288-bit configurations).

The devices perform all the necessary arbitration

to decide which device drives the SRAM Bus. The

latency of the searches increases as the table size

increases while the search rate remains constant.

Depth-Cascading Up to Eight Devices (One

Block)

Figure 93, page 125 shows how up to eight devic-

es can cascade to form a 512K x 72, 256K x 144,

or 128K x 288 bit table. It also shows the intercon-

nection between the devices for depth-cascading.

Each Search Engine asserts the LHO[1] and

LHO[0] signals to inform downstream devices of

its result. The LHI[6:0] signals for a device are con-

nected to LHO signals of the upstream devices.

The host ASIC must program the TLSZ to '01' for

each of up to eight devices in a block. Only a single

device drives the SRAM Bus in any single cycle.

Depth-Cascading Up to 31 Devices (4 Blocks)

Figure 94, page 126 shows how to cascade up to

four blocks. Each block contains up to eight

M7040Ns (except the last block) and the intercon-

nection within each is shown in Figure 93, page

125.

Note: The interconnection between blocks for

depth-cascading is important. For each SEARCH,

a block asserts BHO[2], BHO[1], and BHO[0]. The

BHO[2:0] signals for a block are the signals taken

only from the last device in the block. For all other

devices within that block, these signals stay open

and floating. The host ASIC must program the ta-

ble size (TLSZ) field to '10' in each of the devices

for cascading up to 31 devices (in up to four

blocks).

Depth-Cascading to Generate a “FULL” Signal

Bit[0] of each of the 72-bit entries is designated as

a special bit (1 = occupied; 0 = empty). For each

LEARN or PIO WRITE to the data array, each de-

vice asserts FULO[1] and FULO[0] if it does not

have any empty locations (see Figure 95, page

127).

Each device combines the FULO signals from the

devices above it with its own “full” status to gener-

ate a FULL signal that gives the “full” status of the

table up to the device asserting the FULL signal.

Figure 95, page 127 shows the hardware connec-

tion diagram for generating the FULL signal that

goes back to the ASIC. In a depth-cascaded block

of up to eight devices, the FULL signal from the

last device should be fed back to the ASIC control-

ler to indicate the fullness of the table. The FULL

signal of the other devices should be left open.

Note: The LEARN instruction is supported for only

up to eight devices, whereas FULL cascading is

allowed only for one block in tables containing

more than eight devices. In tables for which a

LEARn instruction is not going to be used, the

Bit[0] of each 72-bit entry should always be set to

'1.'

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