M7040N datasheet(128/159 Pages) STMICROELECTRONICS

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M7040N

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SRAM ADDRESSING

Table 52 describes the commands used to gener-

ate addresses on the SRAM Address Bus. The in-

dex [15:0] field contains the address of a 72-bit

entry that results in a hit in 72-bit-configured quad-

rant. It is the address of the 72-bit entry that lies at

the 144-bit page, and the 288-bit page boundaries

in 144-bit- and 288-bit-configured quadrants, re-

spectively.

REGISTERS, page 22 of this specification, de-

scribes the NFA and SSR Registers. ADR[15:0]

contains the address supplied on the DQ Bus dur-

ing PIO access to the M7040N. Command Bits 8,

7, and 6 {CMD[8:6]} are passed from the com-

mand to the SRAM Address Bus (see COMMAND

CODES AND PARAMETERS, page 30 for more

information). ID[4:0] is the ID of the device driving

the SRAM Bus (see Figure 3, page 9 and Table 2,

page 8 for more information).

Table 52. Generating an SRAM Bus Address

SRAM PIO Access

SRAM READ enables READ access to off-chip

SRAM that contains associative data. The latency

from the issuance of the READ Instruction to the

address appearing on the SRAM Bus is the same

as the latency of the SEARCH Instruction and will

depend on the TLSZ value parameter pro-

grammed in the device Configuration Register.

The latency of the ACK from the READ Instruction

is the same as the latency of the SEARCH Instruc-

tion to the SRAM address plus the HLAT pro-

grammed in the Configuration Register.

Note: SRAM READ is a blocking operation – no

new instruction can begin until the ACK is returned

by the selected device performing the access.

SRAM WRITE enables WRITE access to the off-

chip SRAM containing associative data. The laten-

cy from the second cycle of the WRITE Instruction

to the address appearing on the SRAM Bus is the

same as the latency of the SEARCH Instruction

and will depend on the TLSZ value parameter pro-

grammed in the device Configuration Register.

Note: SRAM WRITE is a pipelined operation –

new instruction can begin right after the previous

command has ended.

SRAM READ with a Table of One Device

SRAM READ enables READ access to the off-

chip SRAM containing associative data. The laten-

cy from the issuance of the READ Instruction to

the address appearing on the SRAM Bus is the

same as the latency of the SEARCH Instruction

and will depend on the TLSZ value parameter pro-

grammed in the device configuration register. The

latency of the ACK from the READ Instruction is

the same as the latency of the SEARCH Instruc-

tion to the SRAM address plus the HLAT pro-

grammed in the configuration register.

The following explains the SRAM READ operation

in a table with only one device that has the follow-

ing parameters: TLSZ = 00, HLAT = 000, LRAM =

1, and LDEV = 1. Figure 96, page 129 shows the

associated timing diagram.

For the following description, the selected device

refers to the only device in the table because it is

the only device to be accessed.

The sequence of the operation is as follows:

– Cycle 1A: The host ASIC applies the READ In-

struction on the CMD[1:0], using CMDV = 1.

The

Bus

supplies

the

address

with

DQ[20:19] set to '10' to select the SRAM ad-

dress. The host ASIC selects the device for

which the ID[4:0] matches the DQ[25:21] lines.

During this cycle, the host ASIC also supplies

SADR[23:21] on CMD[8:6] in this cycle.

– Cycle 1B: The host ASIC continues to apply the

READ Instruction on the CMD[1:0] using

CMDV = 1. The DQ Bus supplies the address

with DQ[20:19] set to '10' to select the SRAM

address.

Command

SRAM Operation

[20:16]

[15:0]

READ

ID[4:0]

Index[15:0]

LEARN

WRITE

ID[4:0]

NFA[15:0]

PIO READ

READ

ID[4:0]

ADR[15:0]

PIO WRITE

WRITE

ID[4:0]

ADR[15:0]

Indirect Access

WRITE/READ

ID[4:0]

SSR[15:0]

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