AT45DB021E datasheet(45/69 Pages) RENESAS

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DS-AT45DB021E-8789 Rev. N

Page 45

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AT45DB021E Datasheet

18. Power-On/Reset State

When power is first applied to the device, or when recovering from a reset condition, the output pin (SO) is in a

high impedance state, and a high-to-low transition on the CSB pin is required to start a valid instruction. The SPI

mode (Mode 3 or Mode 0) is automatically selected on every falling edge of CSB by sampling the inactive clock

state.

18.1 Power-Up/Power-Down Voltage and Timing Requirements

As the device initializes, there is a transient current demand. The system needs to be capable of providing this

current to ensure correct initialization. During power-up, the device must not be READ for at least the minimum

tVCSL time after the supply voltage reaches the minimum VPOR level (VPOR min). While the device is being

powered-up, the internal Power-On Reset (POR) circuitry keeps the device in a reset mode until the supply

voltage rises above the minimum Vcc. During this time, all operations are disabled and the device does not

respond to any commands.

If the first operation to the device after power-up is a program or erase operation, then the operation cannot be

started until the supply voltage reaches the minimum Vcc level and an internal device delay has elapsed. This

delay has a maximum time of tPUW. After the tPUW time, the device is in the standby mode if CSB is at logic high or

active mode if CSB is at logic low. For the case of Power-down then Power-up operation, or if a power interruption

occurs (such that Vcc drops below VPOR max), the Vcc of the Flash device must be maintained below VPWD for at

least the minimum specified TPWD time. This is to ensure the Flash device resets properly after a power

interruption.

Table 33. Voltage and Timing Requirements for Power-Up/Power-Down

Figure 23. Power-Up Timing

Symbol

Parameter

Min

Max

Units

VPWD[1]

1. Not 100% tested (value guaranteed by design and characterization).

VCC for device initialization

1.0

tPWD[1]

Minimum duration for device initialization

300

µs

tVCSL

Minimum VCC to chip select low time for Read command

µs

tVR[1]

VCC rise time

500000

µs/V

VPOR

Power on reset voltage

1.45

1.6

tPUW

Power up delay time before Program or Erase is allowed

VCC

POR max

Max V

PWD

Time

PWD

PUW

Full Operation Permitted

VCSL

Read Operation

Permitted

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