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AT45DB021E Datasheet(PDF) 69 Page - Renesas Technology Corp |
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AT45DB021E Datasheet(HTML) 69 Page - Renesas Technology Corp |
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69 / 69 page ![]() DS-AT45DB021E-8789 Rev. N Page 69 3/24/26 © 2012-2026 Renesas Electronics AT45DB021E Datasheet 8789L 08/2022 Applied Renesas Corporate Template to document. Added the following sentence to the description of CS in Table 1: “To ensure correct power-up sequencing, it is recommended to add a 10k Ohm pull-up resistor from CS to VCC. This ensures CS ramps together with VCC during power-up.” 8789M 04/2024 Changed note from below Table 34 from: “All inputs (SI, SCK, CS, WP, and RESET) are guaranteed by design to be 5V tolerant.” to “All inputs (SI, SCK, CS, WP, and RESET) are guaranteed by design to be 5 V tolerant; however, usage of 5V tolerance for extended periods can effect device reliability.” Removed empty Section 32. Errata. Updated/corrected the Ordering Information in Section 29. Updated PODs in Section 30. 8789N 03/2026 Updated Figure 1 ‘Pinouts.’ Updated Section 30.2 ‘8-lead 208-mil EIAJ SOIC.’ Added new 8-Ball, 1.879 x 1.395 x 0.520 mm WLCSP to Section 30.4. Marked Section 30.5 ‘8-Ball (2 x 4 Array) Wafer Level Chip Scale Package’ as (EOL). Doc. Rev. Date Comments |
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