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AT45DB021E Datasheet(PDF) 18 Page - Renesas Technology Corp

Part # AT45DB021E
Description  2-Mbit DataFlash (with Extra 64 kbits) 1.65 V Minimum SPI Serial Flash Memory
PDF  69 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

AT45DB021E Datasheet(HTML) 18 Page - Renesas Technology Corp

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DS-AT45DB021E-8789 Rev. N
Page 18
3/24/26
© 2012-2026 Renesas Electronics
AT45DB021E Datasheet
When a low-to-high transition occurs on the CS pin, the device erases the selected block of eight pages. The
erase operation is internally self-timed and must take place in a maximum time of tBE. During this time, the
RDY/BUSY bit in the Status Register indicates that the device is busy.
The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase
properly. If an erase error arises, it is indicated by the EPE bit in the Status Register.
8.8
Sector Erase
The Sector Erase command can be used to individually erase any sector in the main memory.
The main memory array is comprised of nine sectors, and only one sector can be erased at a time. To perform an
erase of Sector 0a or Sector 0b with the standard DataFlash page size (264 bytes), an opcode of 7Ch must be
clocked into the device followed by three address bytes comprised of five dummy bits, seven page address bits
(PA9 - PA3), and 12 dummy bits. To perform a Sector 1-7 erase, an opcode of 7Ch must be clocked into the
device followed by three address bytes comprised of five dummy bits, three page address bits (PA9 - PA7), and 16
dummy bits.
To perform a Sector 0a or Sector 0b erase with the binary page size (256 bytes), an opcode of 7Ch must be
clocked into the device followed by three address bytes comprised of six dummy bits, seven page address bits
(A17 - A11), and 11 dummy bits. To perform a Sector 1-7 erase, an opcode of 7Ch must be clocked into the device
followed by six dummy bits, three page address bits (A17 - A15), and 15 dummy bits.
The page address bits are used to specify any valid address location within the sector is to be erased. When a
low-to-high transition occurs on the CS pin, the device erases the selected sector. The erase operation is
internally self-timed and must take place in a maximum time of tSE. During this time, the RDY/BUSY bit in the
Status Register indicates that the device is busy.
The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase
properly. If an erase error arises, it is indicated by the EPE bit in the Status Register.
Table 2. Block Erase Addressing
PA9/A17
PA8/A16
PA7/A15
PA6/A14
PA5/A13
PA4/A12
PA3/A11
PA2/A10
PA1/A9
PA0/A8
Block
000
00
00
X
X
X
0
000
00
01
X
X
X
1
000
00
10
X
X
X
2
000
00
11
X
X
X
3
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
111
11
00
X
X
X
124
111
11
01
X
X
X
125
111
11
10
X
X
X
126
111
11
11
X
X
X
127
Table 3. Sector Erase Addressing
PA9/A17
PA8/A16
PA7/A15
PA6/A14
PA5/A13
PA4/A12
PA3/A11
PA2/A10
PA1/A9
PA0/A8
Sector
000
00
00
X
X
X
0a
000
00
01
X
X
X
0b
0
0
1
XX
XXX
XX
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
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