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ICS853S12 Datasheet(PDF) 1 Page - Renesas Technology Corp |
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ICS853S12 Datasheet(HTML) 1 Page - Renesas Technology Corp |
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1 / 18 page ![]() LOW SKEW, 1-TO-12, DIFFERENTIAL-TO- 3.3V, 2.5V LVPECL FANOUT BUFFER ICS853S12I IDT™ / ICS™ LVPECL FANOUT BUFFER 1 ICS853S12AKI REV. A MAY 21, 2008 GENERAL DESCRIPTION The ICS853S12I is a low skew, 1-to-12 Differential- to-3.3V, 2.5V LVPECL Fanout Buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. The PCLK, nPCLK pair accepts LVPECL, CML, and SSTL differential input levels. The high gain differential amplifier accepts peak-to-peak input voltages as small as 150mV, as long as the common mode voltage is within the specified minimum and maximum range. Guaranteed output and part-to-part skew characteristics make the ICS853S12I ideal for those clock distribution applications demanding well defined performance and repeatability. FEATURES • Twelve differential 3.3V, 2.5V LVPECL outputs • PCLK, nPCLK input pair • PCLK, nPCLK pair can accept the following differential input levels: LVPECL, CML, SSTL • Maximum output frequency: 1.5GHz • Translates any single-ended input signal to 2.5V or 3.3V LVPECL levels with a resistor bias on nPCLK input • Additive phase jitter, RMS: 0.06ps (typical) • Output skew: 50ps (maximum) • Part-to-part skew: 250ps (maximum) • Propagation delay: 680ps (maximum) • Full 3.3V or 2.5V operating supply modes • -40°C to 85°C ambient operating temperature • Available in lead-free (RoHS 6) package BLOCK DIAGRAM PIN ASSIGNMENT HiPerClockS™ ICS 24 23 22 21 20 19 18 17 nQ7 Q7 nQ6 Q6 nQ5 Q5 nQ4 Q4 Q11 nQ11 VEE PCLK nPCLK VEE Q0 nQ0 ICS853S12I 32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 PCLK nPCLK Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5 Q11 nQ11 Q10 nQ10 Q9 nQ9 Q8 nQ8 Q7 nQ7 Q6 nQ6 Pullup/Pulldown Pulldown |
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