IDT™ / ICS™ LVPECL FANOUT BUFFER

12

ICS853S12AKI REV. A MAY 21, 2008

ICS853S12I

LOW SKEW, 1-TO-12, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER

POWER CONSIDERATIONS

This section provides information on power dissipation and junction temperature for the ICS853S12I.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS853S12I is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for V

CC

= 3.3V + 5% = 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

• Power (core)

MAX

= V

CC_MAX

* I

EE_MAX

= 3.465V * 137mA = 474.7mW

• Power (outputs)

MAX

= 32mW/Loaded Output pair

If all outputs are loaded, the total power is 12 * 32mW = 384mW

Total Power

_MAX

(3.465V, with all outputs switching) = 474.7mW + 384mW = 858.7mW

2.

Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the

device. The maximum recommended junction temperature for HiPerClockS

TM devices is 125°C.

The equation for Tj is as follows: Tj =

θ

JA * Pd_total + TA

Tj = Junction Temperature

θ

JA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T

A = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance

θ

JA must be used. Assuming no

air flow and a multi-layer board, the appropriate value is 42.7°C/W per Table 6 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.859W * 42.7°C/W = 121.7°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,

and the type of board (single layer or multi-layer).

θθθθθ

JA

vs. Air Flow (Meter per Second)

0

1

2.5

Multi-Layer PCB, JEDEC Standard Test Boards

42.7°C/W

37.3°C/W

33.5°C/W

TABLE 6. THERMAL RESISTANCE

θθθθθ

JA

FOR

32 LEAD VFQFN, FORCED CONVECTION