AT80SND1C-ROTIL datasheet(95/210 Pages) ATMEL

95 / 210 page

AT8xC51SND1C

4109E–8051–06/03

Suspend/Resume Management

Suspend

The Suspend state can be detected by the USB controller if all the clocks are enabled

and if the USB controller is enabled. The bit SPINT is set by hardware when an idle

state is detected for more than 3 ms. This triggers a USB interrupt if enabled.

In order to reduce current consumption, the firmware can stop the clocks and put the

C51 in Idle or Power-down mode. The Resume detection is still active.

The stop of the 48 MHz clock from the PLL should be done in the following order:

Disable of the 48 MHz clock input of the USB controller by setting to 1 the SUS-

PCLK bit in the USBCON register.

Disable the PLL by clearing the PLLEN bit in the PLLCON register.

Resume

When the USB controller is in Suspend state, the Resume detection is active even if all

the clocks are disabled and if the C51 is in Idle or Power-down mode. The WUPCPU bit

is set by hardware when a non-idle state occurs on the USB bus. This triggers an inter-

rupt if enabled. This interrupt wakes up the CPU from its Idle or Power-down state and

the interrupt function is then executed. The firmware should first enable the 48 MHz

generation and then reset to 0 the SUSPCLK bit in the USBCON register if needed.

The firmware has to clear the SPINT bit in the USBINT register before any other USB

operation in order to wake up the USB controller from its Suspend mode.

The USB controller is then re-activated.

Figure 66. Example of a Suspend/Resume management

USB Controller Init

Detection of a SUSPEND State

SPINT

Set SUSPCLK

Disable PLL

Microcontroller in Power-down

Detection of a RESUME State

WUPCPU

Enable PLL

Clear SUSPCLK

Clear SPINT Bit

Clear WUPCPU Bit

AT80SND1C-ROTIL Datasheet(PDF) 95 Page - ATMEL Corporation