AT80SND1C-ROTIL datasheet(36/210 Pages) ATMEL

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AT8xC51SND1C

4109E–8051–06/03

Interrupt System

The AT8xC51SND1C, like other control-oriented computer architectures, employ a pro-

gram interrupt method. This operation branches to a subroutine and performs some

service in response to the interrupt. When the subroutine completes, execution resumes

at the point where the interrupt occurred. Interrupts may occur as a result of internal

AT8xC51SND1C activity (e.g., timer overflow) or at the initiation of electrical signals

external to the microcontroller (e.g., keyboard). In all cases, interrupt operation is pro-

grammed by the system designer, who determines priority of interrupt service relative to

normal code execution and other interrupt service routines. All of the interrupt sources

are enabled or disabled by the system designer and may be manipulated dynamically.

A typical interrupt event chain occurs as follows:

•

An internal or external device initiates an interrupt-request signal. The

AT8xC51SND1C, latches this event into a flag buffer.

•

The priority of the flag is compared to the priority of other interrupts by the interrupt

handler. A high priority causes the handler to set an interrupt flag.

•

This signals the instruction execution unit to execute a context switch. This context

switch breaks the current flow of instruction sequences. The execution unit

completes the current instruction prior to a save of the program counter (PC) and

reloads the PC with the start address of a software service routine.

•

The software service routine executes assigned tasks and as a final activity

performs a RETI (return from interrupt) instruction. This instruction signals

completion of the interrupt, resets the interrupt-in-progress priority and reloads the

program counter. Program operation then continues from the original point of

interruption.

Table 48. Interrupt System Signals

Six interrupt registers are used to control the interrupt system. 2 8-bit registers are used

to enable separately the interrupt sources: IEN0 and IEN1 registers (see Table 51 and

Table 52).

Four 8-bit registers are used to establish the priority level of the thirteen sources: IPH0,

IPL0, IPH1 and IPL1 registers (see Table 53 to Table 56).

Interrupt System

Priorities

Each of the thirteen interrupt sources on the AT8xC51SND1C can be individually pro-

grammed to one of four priority levels. This is accomplished by one bit in the Interrupt

Priority High registers (IPH0 and IPH1) and one bit in the Interrupt Priority Low registers

(IPL0 and IPL1). This provides each interrupt source four possible priority levels accord-

ing to Table 49.

Signal

Name

Type

Description

Alternate

Function

INT0

External Interrupt 0

See section "External Interrupts", page 39.

P3.2

INT1

External Interrupt 1

See section “External Interrupts”, page 39.

P3.3

KIN3:0

Keyboard Interrupt Inputs

See section “Keyboard Interface”, page 179.

P1.3:0

AT80SND1C-ROTIL Datasheet(PDF) 36 Page - ATMEL Corporation

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