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LNBH221 Datasheet(PDF) 10 Page - STMicroelectronics

Part # LNBH221
Description  Dual LNB supply and control IC with Step-Up converter and I2C interface
PDF  27 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

LNBH221 Datasheet(HTML) 10 Page - STMicroelectronics

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Application information
LNBH221
10/27
Moreover, it is possible to set the Short Circuit Current protection either statically (simple
current clamp) or dynamically by the PCL bit of the I2C SR; when the PCL (Pulsed Current
Limiting) bit is set to LOW, the overcurrent protection circuit works dynamically, as soon as
an overload is detected, the output is shut-down for a time TOFF, typically 900ms.
Simultaneously the OLF bit of the System Register is set to HIGH. After this time has
elapsed, the output is resumed for a time TON=1/10TOFF (typ.). At the end of TON, if the
overload is still detected, the protection circuit will cycle again through TOFF and TON. At the
end of a full TON in which no overload is detected, normal operation is resumed and the OLF
bit is reset to LOW. Typical TON+TOFF time is 990ms and it is determined by an internal
timer. This dynamic operation can greatly reduce the power dissipation in short circuit
condition, still ensuring excellent power-on start up in most conditions. However, there could
be some cases in which an highly capacitive load on the output may cause a difficult start-
up when the dynamic protection is chosen. This can be solved by initiating any power start-
up in static mode (PCL=HIGH) and then switching to the dynamic mode (PCL=LOW) after a
chosen amount of time. When in static mode, the OLF bit goes HIGH when the current
clamp limit is reached and returns LOW when the overload condition is cleared. This IC is
also protected against overheating: when the junction temperature exceeds 150°C (typ.),
the step-up converter and the linear regulator are shut off, and the OTF SR bit is set to
HIGH. Normal operation is resumed and the OTF bit is reset to LOW when the junction is
cooled down to 140°C (typ.).
Note:
(*): External components are needed to comply to bi-directional DiSEqCTM bus hardware
requirements. Full compliance of the whole application to DiSEqCTM specifications is not
implied by the use of this IC.
Note:
NOTICE: DiSEqC is a trademark of EUTELSAT. I2C is a trademark of Philips
Semiconductors.
5.1
I2C Bus Interface (one for each section)
Data transmission from main µP to the LNBH221 and viceversa takes place through the 2
wires I2C bus interface, consisting of the two lines SDA and SCL (pull-up resistors to
positive supply voltage must be externally connected).
5.2
Data validity
As shown in Figure 5., the data on the SDA line must be stable during the high period of the
clock. The HIGH and LOW state of the data line can only change when the clock signal on
the SCL line is LOW.
5.3
Start and stop conditions
As shown in Figure 6. a start condition is a HIGH to LOW transition of the SDA line while
SCL is HIGH.
The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP
conditions must be sent before each START condition.



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